Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44731 )
Change subject: soc/mediatek/mt8192: Limit DRAM calibration frequency count to reduce bootup time ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44731/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/44731/1//COMMIT_MSG@8 PS1, Line 8: Please elaborate on the strategy in the commit message, document how much the time is reduced.
Also, why limit it to three and not less?
https://review.coreboot.org/c/coreboot/+/44731/1/src/soc/mediatek/mt8192/Kco... File src/soc/mediatek/mt8192/Kconfig:
https://review.coreboot.org/c/coreboot/+/44731/1/src/soc/mediatek/mt8192/Kco... PS1, Line 43: options option
https://review.coreboot.org/c/coreboot/+/44731/1/src/soc/mediatek/mt8192/Kco... PS1, Line 44: shu Please elaborate, what this is in the Kconfig option description.
https://review.coreboot.org/c/coreboot/+/44731/1/src/soc/mediatek/mt8192/dra... File src/soc/mediatek/mt8192/dramc_pi_main.c:
https://review.coreboot.org/c/coreboot/+/44731/1/src/soc/mediatek/mt8192/dra... PS1, Line 385: dramc_info("This shu no need do calibration, use shu0 result directly\n"); What is *shu*?