Attention is currently required from: Subrata Banik, Matt DeVillier, Tim Wawrzynczak, Sridhar Siricilla, Lean Sheng Tan, Patrick Rudolph, EricR Lai.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61650 )
Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(3 comments)
Patchset:
PS2:
sadly no, I need more than a basic Intel account to access the EDS docs
checked against doc# 545845
File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/70fe2019_366562b0
PS3, Line 269: void pmc_clear_pmcon_sts(void)
this function is all the same for all platforms using common code, so why exactly do we have to copy-pasta it once again instead of finally moving it to soc/intel/common?
https://review.coreboot.org/c/coreboot/+/61650/comment/d82de472_93d096e8
PS3, Line 276: /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
: * while retaining MS4V write-1-to-clear bit
nit: not a valid comment according to coreboot codestyle docs ;)
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