[coreboot-gerrit] Change in coreboot[master]: soc/intel: Fix SMRAM base MSR

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34730 )

Change subject: soc/intel: Fix SMRAM base MSR
......................................................................

soc/intel: Fix SMRAM base MSR

Previous setting was correct but assumed SMI handler is
always located at the beginning of TSEG. Break the assumption.

Change-Id: I5da1a36fc95f76fa3225498bbac41b2dd4d1dfec
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/cannonlake/smmrelocate.c
M src/soc/intel/icelake/smmrelocate.c
M src/soc/intel/skylake/smmrelocate.c
3 files changed, 6 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/34730/1

diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c
index a0c5077..26951bd 100644
--- a/src/soc/intel/cannonlake/smmrelocate.c
+++ b/src/soc/intel/cannonlake/smmrelocate.c
@@ -192,10 +192,9 @@
    smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c
index bad6b8e..62a8a0d 100644
--- a/src/soc/intel/icelake/smmrelocate.c
+++ b/src/soc/intel/icelake/smmrelocate.c
@@ -191,10 +191,9 @@
    smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */
diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c
index e9ebe00..3595c15 100644
--- a/src/soc/intel/skylake/smmrelocate.c
+++ b/src/soc/intel/skylake/smmrelocate.c
@@ -201,10 +201,9 @@
    smm_subregion(SMM_SUBREGION_IED, &params->ied_base, &params->ied_size);

/* SMRR has 32-bits of valid address aligned to 4KiB. */
-	params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
    params->smrr_base.hi = 0;
-	params->smrr_mask.lo = (~(tseg_size - 1) & rmask)
-		| MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
    params->smrr_mask.hi = 0;

/* The EMRR and UNCORE_EMRR are at IEDBASE + 2MiB */