Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik.
Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83680?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox ......................................................................
soc/intel/adl: Update DCACHE_BSP_STACK_SIZE for Brox
During the stages which use Cache-as-RAM (CAR), coreboot needs more than 1 KiB as configured in DCACHE_BSP_STACK_SIZE. Hence update that config for Brox. For other boards since it is part of RO, update it on need basis.
BUG=None TEST=Build Brox BIOS image and boot to OS.
Change-Id: I723ba1f4289c393fe7376f989d760b26e75b33da Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/alderlake/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/83680/2