yuchi.chen@intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83314?usp=email )
Change subject: add CPU and PCIe definitions for SNR ......................................................................
add CPU and PCIe definitions for SNR
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4 Signed-off-by: Yuchi Chen yuchi.chen@intel.com --- M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/xhci/xhci.c 7 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/1
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index ae58110..e05317a 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -83,5 +83,12 @@ #define CPUID_LUNARLAKE_A0_1 0xb06d0 #define CPUID_LUNARLAKE_A0_2 0xb06d1 #define CPUID_PANTHERLAKE_A0 0xc06c0 +#define CPUID_SNOWRIDGE_A0 0x80660 +#define CPUID_SNOWRIDGE_A1 0x80661 +#define CPUID_SNOWRIDGE_A2 0x80662 +#define CPUID_SNOWRIDGE_A3 0x80663 +#define CPUID_SNOWRIDGE_B0 0x80664 +#define CPUID_SNOWRIDGE_B1 0x80665 +#define CPUID_SNOWRIDGE_C0 0x80667
#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 7c3b55e..555ba31 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3175,6 +3175,7 @@ #define PCI_DID_INTEL_PTL_ESPI_5 0xe405 #define PCI_DID_INTEL_PTL_ESPI_6 0xe406 #define PCI_DID_INTEL_PTL_ESPI_7 0xe407 +#define PCI_DID_INTEL_SNR_LPC 0x18dc
/* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -4337,6 +4338,7 @@ #define PCI_DID_INTEL_LNL_M_ID 0x6400 #define PCI_DID_INTEL_LNL_M_ID_1 0x6410 #define PCI_DID_INTEL_PTL_ID 0xb001 +#define PCI_DID_INTEL_SNR_ID 0x09a2
/* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4411,6 +4413,7 @@ #define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831 #define PCI_DID_INTEL_PTL_XHCI 0xe47d #define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431 +#define PCI_DID_INTEL_SNR_XHCI 0x18d0
/* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4441,6 +4444,7 @@ #define PCI_DID_INTEL_LNL_P2SB2 0xa84c #define PCI_DID_INTEL_PTL_P2SB 0xe420 #define PCI_DID_INTEL_PTL_P2SB2 0xe44c +#define PCI_DID_INTEL_SNR_P2SB 0x18dd
/* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d5cc883..95e52d5 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -95,6 +95,13 @@ { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_C0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_H0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A2, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_A3, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_B1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_SNOWRIDGE_C0, CPUID_EXACT_MATCH_MASK }, CPU_TABLE_END };
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 0b8c722..135e570 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -391,6 +391,7 @@ PCI_DID_INTEL_ADP_M_N_ESPI_30, PCI_DID_INTEL_ADP_M_N_ESPI_31, PCI_DID_INTEL_SPR_ESPI_1, + PCI_DID_INTEL_SNR_LPC, 0 };
diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index e348501..c6cfe3f 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -157,6 +157,7 @@ PCI_DID_INTEL_ADP_M_P2SB, PCI_DID_INTEL_SPR_SP_P2SB, PCI_DID_INTEL_RPP_S_P2SB, + PCI_DID_INTEL_SNR_P2SB, 0, };
diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8e75d7..c26ee65 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -540,6 +540,7 @@ PCI_DID_INTEL_RPL_P_ID_6, PCI_DID_INTEL_RPL_P_ID_7, PCI_DID_INTEL_RPL_P_ID_8, + PCI_DID_INTEL_SNR_ID, 0 };
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index dd4e5de..bc69bc3 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -151,6 +151,7 @@ PCI_DID_INTEL_ADP_S_XHCI, PCI_DID_INTEL_ADP_M_XHCI, PCI_DID_INTEL_RPP_S_XHCI, + PCI_DID_INTEL_SNR_XHCI, 0 };