Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23592
Change subject: cpu/intel/sandybridge: Put stage cache into TSEG ......................................................................
cpu/intel/sandybridge: Put stage cache into TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in contrast with cbmem which remains accessible. Assuming SMM does not touch the cache this is a good region to cache stages.
TESTED on Thinkpad X220: on a cold boot the stage cache gets created and on S3 the cached ramstage gets properly used.
Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 38 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23592/1
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index f16b119..09311d1 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -22,6 +22,7 @@ #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select CPU_INTEL_COMMON + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_CPU_INIT string @@ -35,4 +36,12 @@ hex default 0x800000
+config SMM_RESERVED_SIZE + hex + default 0x100000 + +config IED_REGION_SIZE + hex + default 0x400000 + endif diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 7516e9d..1e04554 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -11,6 +11,9 @@
smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c + cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 594dde1..9a50e2b 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -92,6 +92,26 @@ #define PSS_LATENCY_TRANSITION 10 #define PSS_LATENCY_BUSMASTER 10
+/* Region of SMM space is reserved for multipurpose use. It falls below + * the IED region and above the SMM handler. */ +#define RESERVED_SMM_SIZE CONFIG_SMM_RESERVED_SIZE +#define RESERVED_SMM_OFFSET \ + (CONFIG_SMM_TSEG_SIZE - CONFIG_IED_REGION_SIZE - RESERVED_SMM_SIZE) + +/* Sanity check config options. */ +#if (CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)) +# error "CONFIG_SMM_TSEG_SIZE <= (CONFIG_IED_REGION_SIZE + RESERVED_SMM_SIZE)" +#endif +#if (CONFIG_SMM_TSEG_SIZE < 0x800000) +# error "CONFIG_SMM_TSEG_SIZE must at least be 8MiB" +#endif +#if ((CONFIG_SMM_TSEG_SIZE & (CONFIG_SMM_TSEG_SIZE - 1)) != 0) +# error "CONFIG_SMM_TSEG_SIZE is not a power of 2" +#endif +#if ((CONFIG_IED_REGION_SIZE & (CONFIG_IED_REGION_SIZE - 1)) != 0) +# error "CONFIG_IED_REGION_SIZE is not a power of 2" +#endif + #ifdef __SMM__ /* Lock MSRs */ void intel_model_206ax_finalize_smm(void); diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index da43de0..e80fa31 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -132,6 +132,10 @@ params->ied_base = tsegmb + params->smram_size; params->ied_size = tseg_size - params->smram_size;
+ /* Adjust available SMM handler memory size. */ + if (IS_ENABLED(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM)) + params->smram_size -= CONFIG_SMM_RESERVED_SIZE; + /* SMRR has 32-bits of valid address aligned to 4KiB. */ params->smrr_base.lo = (params->smram_base & rmask) | MTRR_TYPE_WRBACK; params->smrr_base.hi = 0; diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 1f56585..d446049 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -40,7 +40,8 @@ #define IVB_STEP_D0 (BASE_REV_IVB + 6)
/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 + +#define IED_SIZE CONFIG_IED_REGION_SIZE
/* Northbridge BARs */ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */