[coreboot-gerrit] Change in coreboot[master]: mb/supermicro/x11ssm-f: Relocate devicetree FSP settings

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43926 )

Change subject: mb/supermicro/x11ssm-f: Relocate devicetree FSP settings
......................................................................

mb/supermicro/x11ssm-f: Relocate devicetree FSP settings

Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.

Change-Id: I1f2f1421e1a78d149cc4612bdbeba3ee91c42a62
Signed-off-by: Angel Pons 
---
M src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
1 file changed, 13 insertions(+), 11 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/43926/1

diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
index 80d2305..a301abf 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb
@@ -11,13 +11,6 @@
    register "gen1_dec" = "0x007c0a01"	# Super IO SWC
    register "gen2_dec" = "0x000c0ca1"	# IPMI KCS

-	# PCIe configuration
-	register "PcieRpEnable[0]"	= "1"	# Enable PCH PCIe Port 1 / PCH SLOT4
-	register "PcieRpEnable[4]"	= "1"	# Enable PCH PCIe Port 5 / PCH SLOT5
-	register "PcieRpEnable[8]"	= "1"	# Enable PCH PCIe Port 9 / GbE 1
-	register "PcieRpEnable[9]"	= "1"	# Enable PCH PCIe Port 10 / GbE 2
-	register "PcieRpEnable[10]"	= "1"	# Enable PCH PCIe Port 11 / Aspeed 2400 VGA
-
    # USB configuration
    # USB0/1
    register "usb2_ports[5]"	= "USB2_PORT_MID(OC2)"
@@ -52,24 +45,33 @@

device domain 0 on
    	device pci 01.0 on	# CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6)
-			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
+			smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong"
+					 "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
    	end
    	device pci 01.1 on	# CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7)
-			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort"
+					 "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
    	end
    	device pci 1c.0 on	# PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
-			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
+			register "PcieRpEnable[0]"	= "1"
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort"
+					 "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
    	end
    	device pci 1c.4 on	# PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
-			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
+			register "PcieRpEnable[4]"	= "1"
+			smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort"
+					 "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
    	end
    	device pci 1d.0 on	# PCH PCIe Port 9
+			register "PcieRpEnable[8]"	= "1"
    		device pci 00.0 on end	# GbE 1
    	end
    	device pci 1d.1 on	# PCH PCIe Port 10
+			register "PcieRpEnable[9]"	= "1"
    		device pci 00.1 on end	# GbE 2
    	end
    	device pci 1d.2 on	# PCH PCIe Port 11
+			register "PcieRpEnable[10]"	= "1"
    		device pci 00.0 on	# Aspeed PCI Bridge
    			device pci 00.0 on end	# Aspeed 2400 VGA
    		end