build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59193 )
Change subject: WIP libpayload: Parse DDR Information through coreboot tables WIP ......................................................................
Patch Set 1:
(4 comments)
File payloads/libpayload/libc/coreboot.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/1c757a9e_4f7d0845 PS1, Line 357: cb_parse_mem_chip_info(ptr, info); code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/07e6b2c9_f32cc133 PS1, Line 357: cb_parse_mem_chip_info(ptr, info); please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/1ea7b3c3_fdf41090 PS1, Line 358: break; code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-133029): https://review.coreboot.org/c/coreboot/+/59193/comment/97a45a43_2f4885d0 PS1, Line 358: break; please, no spaces at the start of a line