Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39986 )
Change subject: soc/intel/cnl: Configure PcieRpSlotImplemented
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/39986/2//COMMIT_MSG@10
PS2, Line 10: update.
Maybe we could tie it to `smbios_slot_type` in `struct device`, or add
another flag into `struct device`? Having yet another FSP setting in
the devicetree that gets redundant information seems wrong...
--
To view, visit
https://review.coreboot.org/c/coreboot/+/39986
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c
Gerrit-Change-Number: 39986
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Singer
felixsinger@posteo.net
Gerrit-Reviewer: Nico Huber
nico.h@gmx.de
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Tue, 31 Mar 2020 21:22:20 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment