[coreboot-gerrit] Change in coreboot[master]: intel/apollolake: Unify SMM relocation

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34756 )

Change subject: intel/apollolake: Unify SMM relocation
......................................................................

intel/apollolake: Unify SMM relocation

Change-Id: I0ddba64fb65df2e1e0cecd4b446d3a10031ad304
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/apollolake/cpu.c
1 file changed, 32 insertions(+), 29 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/34756/1

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 9b9b722..b117f21 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -132,13 +132,13 @@
 /*
  * MP and SMM loading initialization.
  */
-struct smm_relocation_attrs {
-	uint32_t smbase;
-	uint32_t smrr_base;
-	uint32_t smrr_mask;
+
+struct smm_relocation_params {
+	msr_t smrr_base;
+	msr_t smrr_mask;
 };

-static struct smm_relocation_attrs relo_attrs;
+static struct smm_relocation_params smm_reloc_params;

/*
  * Do essential initialization tasks before APs can be fired up.
@@ -202,46 +202,49 @@
 }
 #endif

+static void fill_in_relocation_params(struct smm_relocation_params *params)
+{
+	uintptr_t tseg_base;
+	size_t tseg_size;
+
+	/* All range registers are aligned to 4KiB */
+	const u32 rmask = ~(4 * KiB - 1);
+
+	smm_region(&tseg_base, &tseg_size);
+
+	/* SMRR has 32-bits of valid address aligned to 4KiB. */
+	params->smrr_base.lo = (tseg_base & rmask) | MTRR_TYPE_WRBACK;
+	params->smrr_base.hi = 0;
+	params->smrr_mask.lo = (~(tseg_size - 1) & rmask) | MTRR_PHYS_MASK_VALID;
+	params->smrr_mask.hi = 0;
+}
+
 static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
    			size_t *smm_save_state_size)
 {
-	uintptr_t smm_base;
-	size_t smm_size;
-	uintptr_t handler_base;
-	size_t handler_size;
+	printk(BIOS_DEBUG, "Setting up SMI for CPU\n");

-	/* All range registers are aligned to 4KiB */
-	const uint32_t rmask = ~((1 << 12) - 1);
+	fill_in_relocation_params(&smm_reloc_params);

-	/* Initialize global tracking state. */
-	smm_region(&smm_base, &smm_size);
-	smm_subregion(SMM_SUBREGION_HANDLER, &handler_base, &handler_size);
+	smm_subregion(SMM_SUBREGION_HANDLER, perm_smbase, perm_smsize);

-	relo_attrs.smbase = smm_base;
-	relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
-	relo_attrs.smrr_mask = ~(smm_size - 1) & rmask;
-	relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
-
-	*perm_smbase = handler_base;
-	*perm_smsize = handler_size;
-	*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
+	*smm_save_state_size = sizeof(em64t101_smm_state_save_area_t);
 }

static void relocation_handler(int cpu, uintptr_t curr_smbase,
    			uintptr_t staggered_smbase)
 {
-	msr_t smrr;
+	struct smm_relocation_params *relo_params = &smm_reloc_params;
    em64t100_smm_state_save_area_t *smm_state;
+
    /* Set up SMRR. */
-	smrr.lo = relo_attrs.smrr_base;
-	smrr.hi = 0;
-	wrmsr(IA32_SMRR_PHYS_BASE, smrr);
-	smrr.lo = relo_attrs.smrr_mask;
-	smrr.hi = 0;
-	wrmsr(IA32_SMRR_PHYS_MASK, smrr);
+	wrmsr(IA32_SMRR_PHYS_BASE, relo_params->smrr_base);
+	wrmsr(IA32_SMRR_PHYS_MASK, relo_params->smrr_mask);
+
    smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
    smm_state->smbase = staggered_smbase;
 }
+
 /*
  * CPU initialization recipe
  *