HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31921
Change subject: src: Drop unused '#include <halt.h>' ......................................................................
src: Drop unused '#include <halt.h>'
Change-Id: Ie7afe77053a21bcf6a1bf314570f897d1791a620 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/commonlib/storage/bouncebuf.c M src/commonlib/storage/sdhci.c M src/cpu/intel/haswell/romstage.c M src/ec/google/chromeec/ec.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/link/romstage.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/stout/romstage.c M src/mainboard/intel/emeraldlake2/romstage.c M src/mainboard/kontron/ktqm77/romstage.c M src/mainboard/samsung/lumpy/romstage.c M src/mainboard/samsung/stumpy/romstage.c M src/northbridge/amd/agesa/family14/state_machine.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/pineview/romstage.c M src/northbridge/intel/sandybridge/romstage.c M src/northbridge/intel/x4x/early_init.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/pmutil.c M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c M src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c M src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/i82801gx/smihandler.c 29 files changed, 7 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31921/1
diff --git a/src/commonlib/storage/bouncebuf.c b/src/commonlib/storage/bouncebuf.c index 6ddfb70..5d98c74 100644 --- a/src/commonlib/storage/bouncebuf.c +++ b/src/commonlib/storage/bouncebuf.c @@ -17,7 +17,6 @@
#include <arch/cache.h> #include "bouncebuf.h" -#include <halt.h> #include "storage.h" #include <string.h> #include <commonlib/stdlib.h> diff --git a/src/commonlib/storage/sdhci.c b/src/commonlib/storage/sdhci.c index 8482488..06dffb1 100644 --- a/src/commonlib/storage/sdhci.c +++ b/src/commonlib/storage/sdhci.c @@ -24,7 +24,6 @@ #include <commonlib/storage.h> #include <delay.h> #include <endian.h> -#include <halt.h> #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1e5f3d3..e64643a 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -21,7 +21,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <halt.h> #include <lib.h> #include <timestamp.h> #include <device/pci_def.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 629144c..57c1b58 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <delay.h> #include <elog.h> -#include <halt.h> #include <reset.h> #include <rtc.h> #include <stdlib.h> diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 726e561..6dfbfcb 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #endif diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 46e2d60..66a503d0 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -27,7 +27,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/common/gpio.h> #include "ec/google/chromeec/ec.h" -#include <halt.h> #include <cbfs.h>
#include <southbridge/intel/bd82x6x/chip.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index ce902be..da6b50d 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -25,7 +25,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include "ec/compal/ene932/ec.h"
void pch_enable_lpc(void) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index f60f822..d76e9c1 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include <bootmode.h> #include <ec/quanta/it8518/ec.h> #include "ec.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index a9b80e8..1259fe8 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -26,7 +26,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h>
#define SIO_PORT 0x164e
diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 6539cde..0ea982c 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -21,7 +21,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> -#include <halt.h> #include <northbridge/intel/sandybridge/raminit_native.h> #include <northbridge/intel/sandybridge/raminit.h> #include <northbridge/intel/sandybridge/sandybridge.h> diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 74d491f..1080689 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -28,7 +28,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #include "option_table.h" #if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 9450aa1..57fdbcb 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#include <halt.h> #if CONFIG(DRIVERS_UART_8250IO) #include <superio/smsc/lpc47n207/lpc47n207.h> #endif diff --git a/src/northbridge/amd/agesa/family14/state_machine.c b/src/northbridge/amd/agesa/family14/state_machine.c index 8db6095..d29656c 100644 --- a/src/northbridge/amd/agesa/family14/state_machine.c +++ b/src/northbridge/amd/agesa/family14/state_machine.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <halt.h> #include <smp/node.h> #include <northbridge/amd/agesa/state_machine.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 11dc203..4f28474 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -21,7 +21,6 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/pci.h> -#include <halt.h> #include <string.h> #include <northbridge/intel/pineview/pineview.h> #include <northbridge/intel/pineview/chip.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 5aea59e..fa5122a 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <cpu/x86/cache.h> #include <delay.h> -#include <halt.h> #include <lib.h> #include "pineview.h" #include "raminit.h" diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 757e272..cf1da63 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <cbmem.h> +#include <halt.h> #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index c979897..d48bac4 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -27,7 +27,6 @@ #include <cpu/intel/romstage.h> #include <device/pci_def.h> #include <device/device.h> -#include <halt.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 5ccc77e..d019ffd 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -26,7 +26,6 @@ #include <pc80/mc146818rtc.h> #include "x4x.h" #include <console/console.h> -#include <halt.h> #include <romstage_handoff.h>
void x4x_early_init(void) diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index dfc5366..62f8e42 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <halt.h> #include <mrc_cache.h> #include <soc/gpio.h> #include <soc/iomap.h> diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 8c166cf..37d1365 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -30,7 +30,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <halt.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 038375b..36a01c6 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -23,13 +23,11 @@ #include <cpu/x86/smm.h> #include <spi-generic.h> #include <elog.h> -#include <halt.h> #include <soc/lpc.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/smm.h>
- /** * @brief Set the EOS bit */ diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index ea9a41b..fa2411d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <halt.h> #include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 5ea0902..b517e6d 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -27,7 +27,6 @@ #include <device/pci_def.h> #include <console/console.h> #include <intelblocks/pmclib.h> -#include <halt.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/tco.h> #include <stdlib.h> diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 65604a1..08ebe98 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -17,7 +17,6 @@ #define SOC_MEDIATEK_MT8183_RTC_H
#include <soc/rtc_common.h> -#include <halt.h>
/* RTC registers */ enum { diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 64eedfb..d67315b 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */
+#include <halt.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/mt6358.h> diff --git a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c index 7cc3204..4f219e4 100644 --- a/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra124/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <halt.h> #include <stdint.h>
/* Function unit addresses. */ diff --git a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c index 51e75f5..ddd1f4f 100644 --- a/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c +++ b/src/soc/nvidia/tegra210/lp0/tegra_lp0_resume.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */
+#include <halt.h> #include <stdint.h>
/* Function unit addresses. */ diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index c7f668b..374a9d9 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -22,11 +22,6 @@ #include <device/pci_def.h> #include <cpu/x86/smm.h> #include <elog.h> -#include <halt.h> -#include "pch.h" - -#include "nvs.h" - #include <northbridge/intel/sandybridge/sandybridge.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> @@ -34,6 +29,9 @@ #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/finalize.h>
+#include "pch.h" +#include "nvs.h" + static global_nvs_t *gnvs; global_nvs_t *smm_get_gnvs(void) { diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index cf7f277..31306fb 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -19,7 +19,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> #include <device/pci_def.h> -#include <halt.h> #include <pc80/mc146818rtc.h> #include <southbridge/intel/common/pmutil.h> #include "i82801gx.h"