[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47837 )

Change subject: soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/47837/1//COMMIT_MSG@14 
PS1, Line 14: MRC training
> hehe, I know that feeling. […]

Yes Angel, it was very weird feeling that none of training is failing bt still system is getting random hang across 😭

This CL helps to reach at much stable boot recipe.