EricKY Cheng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68742 )
Change subject: mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT ......................................................................
mb/google/skyrim/var/winterhold: Update DPTC setting for EVT-SMT
Initialize thermal table config E as default table for EVT-SMT.
BUG=b:232946420 TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng ericky_cheng@compal.corp-partner.google.com Change-Id: I4aa90304e1e7bda7d580de2582129191e9eb0e76 --- M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 1 file changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/68742/1
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb index 900cd23..17e1856 100644 --- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb +++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb @@ -1,6 +1,28 @@ # SPDX-License-Identifier: GPL-2.0-or-later
chip soc/amd/mendocino + + register "system_configuration" = "4" + + # Set DPTC confiuration. Table E (EVT-SMT) + register "thermctl_limit_degreeC" = "97" + register "fast_ppt_limit_mW" = "30000" + register "slow_ppt_limit_mW" = "12000" + register "slow_ppt_time_constant_s" = "5" + register "sustained_power_limit_mW" = "12000" + + # Enable STT support + register "stt_control" = "1" + register "stt_pcb_sensor_count" = "2" + register "stt_min_limit" = "7000" + register "stt_m1" = "0" + register "stt_m2" = "0" + register "stt_c_apu" = "0" + register "stt_alpha_apu" = "0x6666" + register "stt_skin_temp_apu" = "0x3200" + register "stt_error_coeff" = "0x21" + register "stt_error_rate_coefficient" = "0xCCD" + device domain 0 on device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref xhci_1 on # XHCI1 controller