Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, Tim Chu.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81958?usp=email )
Change subject: soc/intel/xeon_sp: Add soc_add_dram_resources
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS1:
@Nico, @Angel, […]
Sorry, it isn't clear. The problem isn't the API itself, it's whether an API is needed at all.
On Gen6, what kind of resource exists between 4G and TOHM? The current patches make coreboot not report anything at all for this range, which feels very wrong (it means Gen6 only has RAM below 4G).
Without knowing anything else about Gen6, I feel it should at least use the non-CXL path in common code:
```
/* 4GiB -> TOHM */
res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1);
LOG_RESOURCE("high_ram", dev, res);
```
This is easily accomplished by not setting `SOC_INTEL_HAS_CXL`, which means this change should be put on hold for now. We shall revisit this when `soc_add_dram_resources` for Gen6 is implemented.
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