Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81956?usp=email )
Change subject: soc/intel/xeon_sp: Set domain0's ACPI name as PCI0 ......................................................................
soc/intel/xeon_sp: Set domain0's ACPI name as PCI0
For Xeon-SP, TPM device is owned by domain0, while src/drivers/ pc80/tpm/tis.c requires the TPM owner name as PCI0 for Windows 11 compliance. Update Xeon-SP codes to follow the current design.
TEST=Build and boot on intel/archercity CRB
Below issue is fixed,
ACPI BIOS Error (bug): Could not resolve symbol [_SB.PCI0], AE_NOT_FOUND (20200925/dswload2-163) ACPI Error: AE_NOT_FOUND, During name lookup/catalog (20200925/psobject-221) ACPI: Skipping parse of AML opcode: OpcodeName unavailable (0x0010)
Change-Id: I26c6a514554f22ff16fd6cce29b8ff4b897c40fb Signed-off-by: Shuo Liu shuo.liu@intel.com --- M src/mainboard/intel/archercity_crb/dsdt.asl M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/spr/acpi/pch.asl M src/soc/intel/xeon_sp/spr/acpi/uncore.asl M src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl 5 files changed, 11 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/81956/1
diff --git a/src/mainboard/intel/archercity_crb/dsdt.asl b/src/mainboard/intel/archercity_crb/dsdt.asl index 2204748..3461c9a 100644 --- a/src/mainboard/intel/archercity_crb/dsdt.asl +++ b/src/mainboard/intel/archercity_crb/dsdt.asl @@ -23,7 +23,7 @@ #include <soc/intel/xeon_sp/spr/acpi/uncore.asl>
// LPC related entries - Scope (_SB.PC00) + Scope (_SB.PCI0) { #include <soc/intel/xeon_sp/spr/acpi/pch.asl> } diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 510d44e..67123fe 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -107,7 +107,10 @@ return;
char *name = xmalloc(ACPI_NAME_BUFFER_SIZE); - snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack); + if (is_domain0(dev)) + snprintf(name, ACPI_NAME_BUFFER_SIZE, "PCI0"); + else + snprintf(name, ACPI_NAME_BUFFER_SIZE, "%s%1X%1X", prefix, dn.socket, dn.stack); dev->name = name; }
diff --git a/src/soc/intel/xeon_sp/spr/acpi/pch.asl b/src/soc/intel/xeon_sp/spr/acpi/pch.asl index 05b7d58..cd4f8b8 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pch.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pch.asl @@ -333,7 +333,7 @@ }) Method (_CRS, 0, Serialized) { - Return (CRS0) /* _SB_.PC00.HPET.CRS0 */ + Return (CRS0) /* _SB_.PCI0.HPET.CRS0 */ } } } diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl index a17d42d..4b67d02 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/uncore.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/uncore.asl @@ -10,11 +10,11 @@ { #include "uncore_irq.asl"
- Device(PC00) + Device(PCI0) { Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) - Name (_UID, "PC00") + Name (_UID, "PCI0") }
#if CONFIG(SOC_ACPI_HEST) diff --git a/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl index 699be7e..9fb96e2 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/uncore_irq.asl @@ -123,18 +123,18 @@ Package(){0x0008FFFF, 2, 0, 18 }, Package(){0x0008FFFF, 3, 0, 19 },
- // [IIM0]: IIOMISC on PC00 + // [IIM0]: IIOMISC on PCI0 Package() { 0x0000FFFF, 0, 0, 16 }, Package() { 0x0000FFFF, 1, 0, 17 }, Package() { 0x0000FFFF, 2, 0, 18 }, Package() { 0x0000FFFF, 3, 0, 19 }, - // [RLK0]: Legacy PCI Express Port 0 on PC00 + // [RLK0]: Legacy PCI Express Port 0 on PCI0 Package() { 0x0003FFFF, 0, 0, 16 }, Package() { 0x0007FFFF, 0, 0, 16 }, })
Name (AR01, Package() { - // [IIM0]: IIOMISC on PCxx(non PC00) + // [IIM0]: IIOMISC on PCxx(non PCI0) Package() { 0x0000FFFF, 0, 0, 16 }, Package() { 0x0000FFFF, 1, 0, 17 }, Package() { 0x0000FFFF, 2, 0, 18 },