Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83850?usp=email )
Change subject: [WIP] soc: Add starfive jh7110 SOC ......................................................................
[WIP] soc: Add starfive jh7110 SOC
Signed-off-by: Maximilian Brune maximilian.brune@9elements.com Change-Id: Ia3104feaf46007e5018a5bbf880d0553ba1fb1de --- A src/soc/starfive/jh7110/Kconfig A src/soc/starfive/jh7110/Makefile.mk A src/soc/starfive/jh7110/bootblock.c A src/soc/starfive/jh7110/cbmem.c A src/soc/starfive/jh7110/chip.c A src/soc/starfive/jh7110/clint.c A src/soc/starfive/jh7110/clock_reset.c A src/soc/starfive/jh7110/gpio.c A src/soc/starfive/jh7110/include/soc/addressmap.h A src/soc/starfive/jh7110/include/soc/clock.h A src/soc/starfive/jh7110/include/soc/gpio.h A src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h A src/soc/starfive/jh7110/include/soc/jh7110.dtsi A src/soc/starfive/jh7110/include/soc/sdram.h A src/soc/starfive/jh7110/memlayout.ld A src/soc/starfive/jh7110/sdram.c A src/soc/starfive/jh7110/uart.c 17 files changed, 5,486 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/83850/1
diff --git a/src/soc/starfive/jh7110/Kconfig b/src/soc/starfive/jh7110/Kconfig new file mode 100644 index 0000000..b67a42a --- /dev/null +++ b/src/soc/starfive/jh7110/Kconfig @@ -0,0 +1,64 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_STARFIVE_JH7110 + bool + select ARCH_RISCV_RV64 + select ARCH_RISCV_S + select ARCH_RISCV_U + select ARCH_RISCV_PMP + select ARCH_BOOTBLOCK_RISCV + select ARCH_VERSTAGE_RISCV + select ARCH_ROMSTAGE_RISCV + select ARCH_RAMSTAGE_RISCV + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select RISCV_USE_ARCH_TIMER + select UART_OVERRIDE_REFCLK + select RISCV_HAS_OPENSBI + +config SEPARATE_ROMSTAGE + default n if SOC_STARFIVE_JH7110 + +if SOC_STARFIVE_JH7110 + +config MEMLAYOUT_LD_FILE + string + default "src/soc/starfive/jh7110/memlayout.ld" + +config RISCV_ARCH + string + default "rv64imac" + +config RISCV_ABI + string + default "lp64" + +config RISCV_CODEMODEL + string + default "medany" + +# 4x U74 cores (RV64IMAFDC) + 1x S7 core (RV64IMAC) +config MAX_CPUS + int + default 5 + +config RISCV_WORKING_HARTID + int + default 1 # use U7 core as S7 core does not support supervisor mode + +config OPENSBI_PLATFORM + string + default "generic" + +config OPENSBI_TEXT_START + hex + default 0x40000000 + +config OPENSBI_FW_DYNAMIC_BOOT_HART + int + default 1 + help + Choose the first U74 core as boot hart since + hart 0 is the S7 which does not support Supervisor mode + +endif diff --git a/src/soc/starfive/jh7110/Makefile.mk b/src/soc/starfive/jh7110/Makefile.mk new file mode 100644 index 0000000..5b1b081 --- /dev/null +++ b/src/soc/starfive/jh7110/Makefile.mk @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_STARFIVE_JH7110),y) + +CPPFLAGS_common += -I src/soc/starfive/jh7110/include +CPPFLAGS_dts += -I src/soc/starfive/jh7110/include + +bootblock-y += bootblock.c +bootblock-y += uart.c +bootblock-y += clint.c + +romstage-y += gpio.c +romstage-y += clock_reset.c +romstage-y += clint.c +romstage-y += uart.c +romstage-y += cbmem.c +romstage-y += sdram.c + +ramstage-y += uart.c +ramstage-y += clint.c +ramstage-y += sdram.c +ramstage-y += cbmem.c +ramstage-y += clock_reset.c +ramstage-y += chip.c + +spl-tool = util/riscv/starfive-jh7110-spl-tool +$(spl-tool)/spl_tool: + $(MAKE) -C $(spl-tool) + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(spl-tool)/spl_tool + @printf " GPT $(notdir $(@))\n" + @$(spl-tool)/spl_tool -c -f $< + cp $<.normal.out $@ #TODO fix tooling + +endif diff --git a/src/soc/starfive/jh7110/bootblock.c b/src/soc/starfive/jh7110/bootblock.c new file mode 100644 index 0000000..d0736ee --- /dev/null +++ b/src/soc/starfive/jh7110/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/encoding.h> +#include <bootblock_common.h> + +void bootblock_soc_early_init(void) +{ + write_csr(0x7c1, 0); // CSR_U74_FEATURE_DISABLE (enable all Features) +} diff --git a/src/soc/starfive/jh7110/cbmem.c b/src/soc/starfive/jh7110/cbmem.c new file mode 100644 index 0000000..a3e369b --- /dev/null +++ b/src/soc/starfive/jh7110/cbmem.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> + +uintptr_t cbmem_top_chipset(void) +{ + return (uintptr_t)JH7110_DRAM + sdram_size(); +} diff --git a/src/soc/starfive/jh7110/chip.c b/src/soc/starfive/jh7110/chip.c new file mode 100644 index 0000000..f4c9a11 --- /dev/null +++ b/src/soc/starfive/jh7110/chip.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbmem.h> +#include <device/device.h> +#include <soc/addressmap.h> +#include <symbols.h> + +static void jh7110_read_resources(struct device *dev) +{ + int index = 0; + ram_from_to(dev, index++, JH7110_DRAM, (uintptr_t)cbmem_top()); +} + +struct device_operations jh7110_cpu_ops = { + .read_resources = jh7110_read_resources, +}; + +struct chip_operations soc_starfive_jh7110_ops = { + .name = "STARFIVE JH7110", +}; diff --git a/src/soc/starfive/jh7110/clint.c b/src/soc/starfive/jh7110/clint.c new file mode 100644 index 0000000..a19c207 --- /dev/null +++ b/src/soc/starfive/jh7110/clint.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mcall.h> +#include <stdint.h> +#include <device/mmio.h> +#include <soc/addressmap.h> + +#define CLINT_MTIME 0xBFF8 +#define CLINT_MTIMECMP 0x4000 + +void mtime_init(void) +{ + long hart_id = read_csr(mhartid); + HLS()->time = (uint64_t *)(JH7110_CLINT + CLINT_MTIME); + HLS()->timecmp = (uint64_t *)(JH7110_CLINT + CLINT_MTIMECMP + 8 * hart_id); +} + +void set_msip(int hartid, int val) +{ + write32((void *)(JH7110_CLINT + 4 * (uintptr_t)hartid), !!val); +} diff --git a/src/soc/starfive/jh7110/clock_reset.c b/src/soc/starfive/jh7110/clock_reset.c new file mode 100644 index 0000000..695c39c --- /dev/null +++ b/src/soc/starfive/jh7110/clock_reset.c @@ -0,0 +1,419 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 Starfive, Inc. + * Author: yanhong yanhong.wang@starfivetech.com + * + * The GMAC0 and GMAC1 settings have been copied from starfives u-boot fork + */ + +// This file is used for setting up clocks and get devices out of reset + +#include <device/mmio.h> +#include <stdint.h> +#include <soc/addressmap.h> +#include <delay.h> +#include <soc/clock.h> +#include <halt.h> + +#define AON_IOMUX_CFG JH7110_AON_GPIO // AON (Always on) multiplexing configuration +#define SYS_IOMUX_CFG JH7110_SYS_IOMUX + +// =============================================== +// SYS CRG registers +// =============================================== + +#define CLK_MUX_SHIFT 24 +#define CLK_MUX_MASK (0x3F << CLK_MUX_SHIFT) //TODO use GENMASK + +#define CLK_ENABLE_SHIFT 31 +#define CLK_ENABLE_MASK (1 << CLK_ENABLE_SHIFT) + +#define CLK_DIV_MASK GENMASK(23, 0) + +// clock enable, divisor and multiplexer register + +#define CLK_CPU_ROOT_OFFSET JH7110_SYS_CRG(0x0) +# define CLK_CPU_ROOT_OSC 0 +# define CLK_CPU_ROOT_PLL0 1 + +#define CLK_CPU_CORE_OFFSET JH7110_SYS_CRG(0x4) + +#define CLK_CPU_BUS_OFFSET JH7110_SYS_CRG(0x8) + +#define CLK_GPU_ROOT_OFFSET JH7110_SYS_CRG(0xc) +# define CLK_GPU_ROOT_PLL2 0 +# define CLK_GPU_ROOT_PLL1 1 + +#define CLK_PERIPHERAL_ROOT_OFFSET JH7110_SYS_CRG(0x10) +# define CLK_PERIPHERAL_ROOT_PLL0 0 +# define CLK_PERIPHERAL_ROOT_PLL2 1 + +#define CLK_BUS_ROOT_OFFSET JH7110_SYS_CRG(0x14) +# define CLK_BUS_ROOT_OSC 0 +# define CLK_BUS_ROOT_PLL2 1 + +#define CLK_PERH_ROOT_OFFSET JH7110_SYS_CRG(0x14) +# define CLK_PERH_ROOT_MASK CLK_MUX_MASK + +#define CLK_DDR_BUS JH7110_SYS_CRG(0xac) +#define CLK_DDR_BUS_MASK CLK_MUX_MASK +# define CLK_DDR_BUS_OSC_DIV2 0 +# define CLK_DDR_BUS_PLL1_DIV2 1 +# define CLK_DDR_BUS_PLL1_DIV4 2 +# define CLK_DDR_BUS_PLL1_DIV8 3 + +#define CLK_STG_MTRX_GROUP_0_MAIN_OFFSET JH7110_SYS_CRG(0x44) +#define CLK_STG_MTRX_GROUP_0_BUS_OFFSET JH7110_SYS_CRG(0x48) +#define CLK_STG_MTRX_GROUP_0_STG_OFFSET JH7110_SYS_CRG(0x4c) +#define CLK_STG_MTRX_GROUP_1_MAIN_OFFSET JH7110_SYS_CRG(0x50) +#define CLK_STG_MTRX_GROUP_1_BUS_OFFSET JH7110_SYS_CRG(0x54) +#define CLK_STG_MTRX_GROUP_1_STG_OFFSET JH7110_SYS_CRG(0x58) +#define CLK_STG_MTRX_GROUP_1_HIFI_OFFSET JH7110_SYS_CRG(0x5c) +#define CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI JH7110_SYS_CRG(0x9c) + +#define CLK_QSPI_OFFSET JH7110_SYS_CRG(0x168) +# define CLK_QSPI_OSC 0 +# define CLK_QSPI_QSPI_REF_SRC 1 + +#define CLK_NOC_STG_AXI_OFFSET JH7110_SYS_CRG(0x180) +#define CLK_TIMER_APB_OFFSET JH7110_SYS_CRG(0x1F0) +#define CLK_TIMER_0_OFFSET JH7110_SYS_CRG(0x1F4) +#define CLK_TIMER_1_OFFSET JH7110_SYS_CRG(0x1F8) +#define CLK_TIMER_2_OFFSET JH7110_SYS_CRG(0x1FC) +#define CLK_TIMER_3_OFFSET JH7110_SYS_CRG(0x200) +#define CLK_UART0_APB_OFFSET JH7110_SYS_CRG(0x244) +#define CLK_UART0_CORE_OFFSET JH7110_SYS_CRG(0x248) + +// reset asser/deassert register + +#define SOFTWARE_RESET_3_OFFSET JH7110_SYS_CRG(0x304) +#define RESET_STATUS_3_OFFSET JH7110_SYS_CRG(0x314) +# define SI5_TIMER_RSTN_APB_SHIFT 21 +# define SI5_TIMER_RSTN_TIMER0_SHIFT 22 +# define SI5_TIMER_RSTN_TIMER1_SHIFT 23 +# define SI5_TIMER_RSTN_TIMER2_SHIFT 24 +# define SI5_TIMER_RSTN_TIMER3_SHIFT 25 + +// reset status registers + +#define SYS_CRG_RESET0 JH7110_SYS_CRG(0x308) +# define RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT 6 // Advanced Extensible Interface +# define RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT 7 +# define RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT 8 // Advanced Peripheral Bus +#define SYS_CRG_RESET1 JH7110_SYS_CRG(0x30c) +#define SYS_CRG_RESET2 JH7110_SYS_CRG(0x310) +#define SYS_CRG_RESET3 JH7110_SYS_CRG(0x314) + +// =============================================== +// AON CRG (Always ON configuration register) +// =============================================== + +#define CLK_AON_APB_OFFSET JH7110_AON_CRG(0x4) +# define CLK_AON_APB_OSC_DIV4 0 +# define CLK_AON_APB_OSC 1 + +// =============================================== +// PLL (Phased Locked Loop) +// =============================================== + + +#define PLL0_PD_OFFSET JH7110_SYS_SYSCONSAIF_SYSCFG(32) //TODO from TRM and u-boot (according to Linux its 0x18) +#define PLL0_PD_MASK BIT(27) +#define PLL0_DACPD_MASK BIT(24) +#define PLL0_DSMPD_MASK BIT(25) +#define PLL0_FBDIV_SHIFT 0 +#define PLL0_FBDIV_MASK GENMASK(11, 0) +#define PLL0_PREDIV_SHIFT 0 +#define PLL0_PREDIV_MASK GENMASK(5, 0) +#define PLL0_POSTDIV1_SHIFT 28 +#define PLL0_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL1_PD_MASK BIT(27) +#define PLL1_DACPD_MASK BIT(15) +#define PLL1_DSMPD_MASK BIT(16) +#define PLL1_FBDIV_SHIFT 17 +#define PLL1_FBDIV_MASK GENMASK(28, 17) +#define PLL1_PREDIV_SHIFT 0 +#define PLL1_PREDIV_MASK GENMASK(5, 0) +#define PLL1_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL2_PD_MASK BIT(27) +#define PLL2_DACPD_MASK BIT(15) +#define PLL2_DSMPD_MASK BIT(16) +#define PLL2_FBDIV_SHIFT 17 +#define PLL2_FBDIV_MASK GENMASK(28, 17) +#define PLL2_PREDIV_SHIFT 0 +#define PLL2_PREDIV_MASK GENMASK(5, 0) +#define PLL2_POSTDIV1_MASK GENMASK(29, 28) + +#define PLL_PD_OFF 1 +#define PLL_PD_ON 0 + +// =============== +// other +// =============== + + +// source clock for all 3 system PLLs from external oszilator +#define REFCLK (24*1000*1000) + +struct jh7110_pll { + //u64 rate; // output frequency in Hz (= REFCLK / prediv * fbdiv) + u32 prediv; // PLL pre divider (dividing REFCLK) + u32 fbdiv; // PLL integer feedback divider + u32 frac; // PLL fractional feedback divider (only used in Fraction Multiple Mode) + //u32 postdiv1; // PLL post divider 1 + //u32 postdiv2; // PLL post divider 2 +}; + +static const struct jh7110_pll jh7110_pll0_tbl[] = { + { .prediv = 8, .fbdiv = 125 }, // 375000000 Hz = 375 MHz + { .prediv = 6, .fbdiv = 125 }, // 500000000 Hz = 500 MHz + { .prediv = 24, .fbdiv = 625 }, // 625000000 Hz = 625 MHz + { .prediv = 4, .fbdiv = 125 }, // 750000000 Hz = 750 MHz + { .prediv = 24, .fbdiv = 875 }, // 875000000 Hz = 875 MHz + { .prediv = 3, .fbdiv = 125 }, // 1000000000 Hz = 1000 MHz + { .prediv = 12, .fbdiv = 625 }, // 1250000000 Hz = 1250 MHz + { .prediv = 24, .fbdiv = 1375 }, // 1375000000 Hz = 1375 MHz + { .prediv = 2, .fbdiv = 125 }, // 1500000000 Hz = 1500 MHz + { .prediv = 24, .fbdiv = 1625 }, // 1625000000 Hz = 1625 MHz + { .prediv = 12, .fbdiv = 875 }, // 1750000000 Hz = 1750 MHz + { .prediv = 3, .fbdiv = 225 }, // 1800000000 Hz = 1800 MHz +}; + +static const struct jh7110_pll jh7110_pll1_tbl[] = { + { .prediv = 12, .fbdiv = 533 }, // 1066000000 Hz = 1066 MHz + { .prediv = 1, .fbdiv = 50 }, // 1200000000 Hz = 1200 MHz + { .prediv = 6, .fbdiv = 350 }, // 1400000000 Hz = 1400 MHz + { .prediv = 3, .fbdiv = 200 }, // 1600000000 Hz = 1600 MHz +}; + +static const struct jh7110_pll jh7110_pll2_tbl[] = { + { .prediv = 2, .fbdiv = 99 }, // 1188000000 Hz = 1188 MHz + { .prediv = 15, .fbdiv = 768 }, // 1228800000 Hz = 1228.8 MHz +}; + +static void clk_set_mux(uint32_t reg, int mux) +{ + clrsetbits32p(reg, CLK_MUX_MASK, (mux << CLK_MUX_SHIFT)); +} + +static void clk_set_div(uint32_t reg, int div) +{ + clrsetbits32p(reg, CLK_DIV_MASK, div); +} + +static void clk_enable(uint32_t reg) +{ + clrsetbits32p(reg, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); +} + +static void jh7110_pll2_set_rate(struct jh7110_pll pll) +{ + //// Before changing PLL2 set GPU (clk_gpu_root) to use PLL1 instead of PLL2 + //clrsetbits32p(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_MASK, 0); + + //// Before changing PLL2 set clk_bus_root to use 24MHz Oscilator instead of PLL2 + //clrsetbits32p(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_MASK, 0); + + //// Before changing PLL2 set clk_perh_root (peripheral clock) to use PLL0 instead of PLL2 + //clrsetbits32p(CLK_PERH_ROOT_OFFSET, CLK_PERH_ROOT_MASK, 0); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL2_FBDIV_MASK, (pll.fbdiv << PLL2_FBDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_POSTDIV1_MASK, 0); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(52), PLL2_PREDIV_MASK, (pll.prediv << PLL2_PREDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(48), PLL2_PD_MASK, PLL_PD_ON); + + //// Set clk_perh_root to use PLL2 again + //clrsetbits32p(CLK_PERH_ROOT_OFFSET, CLK_PERH_ROOT_MASK, (1 << CLK_PERH_ROOT_SHIFT)); + + //// Set clk_bus_root to use PLL2 again + //clrsetbits32p(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_MASK, (1 << CLK_BUS_ROOT_SHIFT)); + + //// Set GPU to use PLL2 again + //clrsetbits32p(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_MASK, (1 << CLK_GPU_ROOT_SHIFT)); +} + +static void jh7110_pll1_set_rate(struct jh7110_pll pll) +{ + // switch DDR clock to external oszillator before configuring PLL1 + clk_set_mux(CLK_DDR_BUS, CLK_DDR_BUS_OSC_DIV2); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(40), PLL1_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_FBDIV_MASK, (pll.fbdiv << PLL1_FBDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(40), PLL1_POSTDIV1_MASK, 0); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(44), PLL1_PREDIV_MASK, (pll.prediv << PLL1_PREDIV_SHIFT)); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL1_PD_MASK, PLL_PD_ON); + + // wait before switching DDR clock back to PLL1 + udelay(100); //TODO check timing + clk_set_mux(CLK_DDR_BUS, CLK_DDR_BUS_PLL1_DIV2); +} + +static void jh7110_pll0_set_rate(struct jh7110_pll pll) +{ + // Before changing PLL0 set CPU to use the 24MHz Oscilator instead of PLL0 + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_OSC); + + // values on reset (tested): fbdiv: 83, prediv: 1, postdiv: 1 + //uint32_t fbdiv = read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(28)) & JH7110_PLL0_FBDIV_MASK; + //uint32_t prediv = read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36)) & JH7110_PLL0_PREDIV_MASK; + //uint32_t postdiv = (read32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32)) & JH7110_PLL0_POSTDIV1_MASK) >> JH7110_PLL0_POSTDIV1_SHIFT; + //die("fbdiv: %d, prediv: %d, postdiv: %d\n", fbdiv, prediv, postdiv); + + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_PD_MASK, PLL_PD_OFF); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(24), PLL0_DACPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(24), PLL0_DSMPD_MASK, 1); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(28), PLL0_FBDIV_MASK, pll.fbdiv << PLL0_FBDIV_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_POSTDIV1_MASK, 1 << PLL0_POSTDIV1_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(36), PLL0_PREDIV_MASK, pll.prediv << PLL0_PREDIV_SHIFT); + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(32), PLL0_PD_MASK, PLL_PD_ON); + + // Set CPU clock divider to 1 + clk_set_div(CLK_CPU_CORE_OFFSET, 1); + // Set CPU to use PLL0 + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_PLL0); +} + +static void clock_pll_init(void) +{ + jh7110_pll0_set_rate(jh7110_pll0_tbl[5]); // 1000 MHz + jh7110_pll1_set_rate(jh7110_pll1_tbl[0]); // 1066 MHz + jh7110_pll2_set_rate(jh7110_pll2_tbl[1]); // 1188 MHz +} + +// enable STG MTRX clocks (TODO what is STG_MTRX?) +static void clk_stg_mtrx(void) +{ + clrsetbits32p(CLK_STG_MTRX_GROUP_0_MAIN_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_0_BUS_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_0_STG_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + clrsetbits32p(CLK_STG_MTRX_GROUP_1_MAIN_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_BUS_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_STG_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_STG_MTRX_GROUP_1_HIFI_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); +} + +static void clk_cpu_root(void) +{ + // init cpu clock + clk_set_mux(CLK_CPU_ROOT_OFFSET, CLK_CPU_ROOT_PLL0); + clk_set_div(CLK_CPU_CORE_OFFSET, 1); + clk_set_div(CLK_CPU_BUS_OFFSET, 2); + + clk_stg_mtrx(); +} + +static void clk_ddr_root(void) +{ +} + +static void clk_gpu_root(void) +{ + clk_set_mux(CLK_GPU_ROOT_OFFSET, CLK_GPU_ROOT_PLL2); +} + +static void clk_bus_root(void) +{ + clk_set_mux(CLK_BUS_ROOT_OFFSET, CLK_BUS_ROOT_PLL2); + + // enable clk_axi_cfg0 (not sure if that is the correct register) + clk_enable(CLK_U0_SFT7110_NOC_BUS_CLK_AXICFG0_AXI); +} + +static void clk_perh_root(void) +{ + clk_set_mux(CLK_PERIPHERAL_ROOT_OFFSET, CLK_PERIPHERAL_ROOT_PLL2); + + // not really sure if these are part of the peripheral root. + // it is also not clear where they belong in the clock structure of the TRM + clk_enable(CLK_NOC_STG_AXI_OFFSET); + clk_set_mux(CLK_AON_APB_OFFSET, CLK_AON_APB_OSC); + clk_set_mux(CLK_QSPI_OFFSET, CLK_QSPI_QSPI_REF_SRC); + //clk_set_div(CLK_QSPI_OFFSET, 10); TODO try smaller divider for faster QSPI access + clk_enable(CLK_QSPI_OFFSET); +} + +void clock_init(void) +{ + // CPU freq: 1250MHz (should be current) + // DDR clk: 2133M (8GB) + // idcode: 0x1860C8 + + clock_pll_init(); + + // the names of the functions are references to the clock structure figure in the TRM + + clk_cpu_root(); + + clk_ddr_root(); + // put DDR into reset + setbits32p(SYS_CRG_RESET1, (1 << RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT)); + + // get DDR out of reset + clrbits32p(SYS_CRG_RESET1, (1 << RSTN_U0_DDR_SFT7110_RSTN_AXI_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_OSC_SHIFT) + || (1 << RSTN_U0_DDR_SFT7110_RSTN_APB_SHIFT)); + + clk_gpu_root(); + + clk_bus_root(); + + //clk_venc_root(); + + //clk_vdec_root(); + + //clk_gmacusb_root(); + + //clk_audio_root(); + + clk_perh_root(); + + //clk_isp_root(); + + //clk_vout_root(); + + // set GPIO to 3.3V + clrsetbits32p(JH7110_SYS_SYSCONSAIF_SYSCFG(12), 0xF, 0x0); + + // Improved GMAC0 TX I/O PAD capability + clrsetbits32p(AON_IOMUX_CFG + 0x78, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x7c, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x80, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x84, 0x3, BIT(0) & 0x3); + clrsetbits32p(AON_IOMUX_CFG + 0x88, 0x3, BIT(0) & 0x3); + + // Improved GMAC1 TX I/O PAD capability + clrsetbits32p(SYS_IOMUX_CFG + 0x26c, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x270, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x274, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x278, 0x3, BIT(0) & 0x3); + clrsetbits32p(SYS_IOMUX_CFG + 0x27c, 0x3, BIT(0) & 0x3); + + // enable UART clock + clrsetbits32p(CLK_UART0_APB_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_UART0_CORE_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + // TODO timer_init(); + // enable clocks for timer + clrsetbits32p(CLK_TIMER_APB_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_0_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_1_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_2_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + clrsetbits32p(CLK_TIMER_3_OFFSET, CLK_ENABLE_MASK, 1 << CLK_ENABLE_SHIFT); + + // pull timer out of reset + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_APB_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER0_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER1_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER2_SHIFT); + clrbits32p(SOFTWARE_RESET_3_OFFSET, SI5_TIMER_RSTN_TIMER3_SHIFT); +} diff --git a/src/soc/starfive/jh7110/gpio.c b/src/soc/starfive/jh7110/gpio.c new file mode 100644 index 0000000..1a56286 --- /dev/null +++ b/src/soc/starfive/jh7110/gpio.c @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/jh7110-pinfunc.h> +#include <stdint.h> +#include <arch/mmio.h> +#include <delay.h> +#include <assert.h> +#include <device/mmio.h> + +// SYS IOMUX CFG +#define SYS_IOMUX_CFG JH7110_SYS_IOMUX +// SYS IOMUX CFGSAIF FMUX +#define SYS_IOMUX_CFGSAIF_FMUX(x) (SYS_IOMUX_CFG + x * 4) +// SYS IOMUX CFGSAIF SYSCFG IOIRQ +#define SYS_IOMUX_CFGSAIF_SYSCFG_IOIRQ(x) (SYS_IOMUX_CFG + x * 4) +// SYS IOMUX CFGSAIF SYSCFG +#define SYS_IOMUX_CFGSAIF_SYSCFG(x) (SYS_IOMUX_CFG + x) + +#define NR_GPIOS 64 + +#define GPIO_DOEN 0x0 +#define GPIO_DOUT 0x40 +#define GPIO_GPI 0x80 +#define GPIO_GPIOIN 0x118 + +void gpio_config_padcfg(u32 port, u32 padcfg) +{ + write32p(SYS_IOMUX_CFGSAIF_SYSCFG(288), padcfg & 0xFF); +} + +void gpio_config(struct gpio_config config) +{ + uintptr_t reg_shift = 8 * (config.port % 4); + uintptr_t reg_offset = 4 * (config.port / 4); + + u32 doen = config.doen << reg_shift; + u32 dout = config.dout << reg_shift; + + u32 doen_mask = 0x3f << reg_shift; + u32 dout_mask = 0x7f << reg_shift; + + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOEN + reg_offset), doen_mask, doen & doen_mask); + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOUT + reg_offset), dout_mask, dout & dout_mask); + + if (config.gpi != GPI_NONE) { + reg_shift = 8 * (config.gpi % 4); + reg_offset = 4 * (config.gpi / 4); + + u32 gpi_mask = 0x7f << reg_shift; + u32 gpi = (config.port + 2) << reg_shift; + + clrsetbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_GPI + reg_offset), gpi_mask, gpi & gpi_mask); + } +} + +//void gpio_set(gpio_t port, int high) +//{ +// +// unintptr_t reg_shift = 8 * (port % 4); +// uintptr_t reg_offset = 4 * (port / 4); +// u32 dout_mask = 0x7f << reg_shift; +// u32 dout = high ? (1 << reg_shift) : 0; +// +// setbits_le32((u32 *)(JH7110_SYS_IOMUX + GPIO_DOUT + reg_offset), dout & dout_mask); +//} +// +//u32 gpio_get(gpio_t port) +//{ +// uintptr_t reg_mask = (port % 32); +// uintptr_t reg_offset = 4 * (port / 32); +// +// u32 val = read32p(JH7110_SYS_IOMUX + GPIO_GPIOIN + reg_offset); +// +// return !!(val & reg_mask); +//} diff --git a/src/soc/starfive/jh7110/include/soc/addressmap.h b/src/soc/starfive/jh7110/include/soc/addressmap.h new file mode 100644 index 0000000..8cd1ab47 --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/addressmap.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_ADDRESSMAP_H__ +#define __SOC_STARFIVE_JH7110_ADDRESSMAP_H__ + +#define JH7110_CLINT 0x02000000 +#define JH7110_L2LIM 0x08000000 +#define JH7110_UART0 0x10000000 +#define JH7110_UART1 0x10010000 +#define JH7110_UART2 0x10020000 +#define JH7110_QSPI 0x21000000 +#define JH7110_SPI0 0x10060000 +#define JH7110_SPI1 0x10070000 +#define JH7110_SPI2 0x10080000 +#define JH7110_SPI3 0x12070000 +#define JH7110_SPI4 0x12080000 +#define JH7110_SPI5 0x12090000 +#define JH7110_SPI6 0x120A0000 +#define JH7110_DRAM 0x40000000 + +#define JH7110_UART(i) (JH7110_UART0 + 0x1000 * i) + +#define JH7110_BOOT_MODE_SELECT_REG 0x1702002C +#define JH7110_BOOT_MODE_SELECT_MASK 0x3 +# define BOOT_MODE_SELECT_SPI 0 +# define BOOT_MODE_SELECT_MMC2 1 +# define BOOT_MODE_SELECT_MMC1 2 +# define BOOT_MODE_SELECT_UART 3 + +// STG (System-Top-Group) controller +#define STG_SYSCON 0x10240000 +// syscon (system control registers) +#define JH7110_SYSCON 0x13030000 +#define JH7110_SYS_SYSCONSAIF_SYSCFG(i) (JH7110_SYSCON + i) +// syscrg (system control and reset generator) +#define JH7110_SYS_CRG(i) (0x13020000 + i) + + +//TODO remove +# define JH7110_SYSCONSAIF_SYSCFG_32_OFFSET 0x20 +# define JH7110_SYSCONSAIF_U0_PLL_WRAP_PLL0_LOCK_SHIFT 26 +# define JH7110_SYSCONSAIF_U0_PLL_WRAP_PLL0_PD_SHIFT 27 +#define JH7110_SYS_IOMUX 0x13040000 +#define JH7110_AON_CRG(i) (0x17000000 + i) +#define JH7110_AON_SYSCON 0x17010000 +#define JH7110_AON_GPIO 0x17020000 // AON (Always on) multiplexing configuration + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/clock.h b/src/soc/starfive/jh7110/include/soc/clock.h new file mode 100644 index 0000000..6c55a5a --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/clock.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_CLOCK_H__ +#define __SOC_STARFIVE_JH7110_CLOCK_H__ + +void clock_init(void); +void jh7110_pll_init(void); +int clock_get_pclk(void); + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/gpio.h b/src/soc/starfive/jh7110/include/soc/gpio.h new file mode 100644 index 0000000..40fadb6 --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/gpio.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_GPIO_H__ +#define __SOC_STARFIVE_JH7110_GPIO_H__ + +#include <stdint.h> +#include <stdbool.h> + +#define GPIO_DOEN_MASK 0x3F +#define GPIO_DOUT_MASK 0x7F +#define GPIO_DIN_MASK 0x7F + +#define GPIO_IE_SHIFT 0 +#define GPIO_IE_MASK BIT(0) +#define GPIO_DS_SHIFT 1 +#define GPIO_DS_MASK GENMASK(2, 1) +#define GPIO_PU_SHIFT 3 +#define GPIO_PU_MASK BIT(3) +#define GPIO_PD_SHIFT 4 +#define GPIO_PD_MASK BIT(4) +#define GPIO_SLEW_SHIFT 5 +#define GPIO_SLEW_MASK BIT(5) +#define GPIO_SMT_SHIFT 6 +#define GPIO_SMT_MASK BIT(6) +#define GPIO_POS_SHIFT 7 +#define GPIO_POS_MASK BIT(7) + +enum gpio_drive_strength { + GPIO_DS_2 = 0, // 2mA + GPIO_DS_4 = 1, // 4mA + GPIO_DS_8 = 2, // 8mA + GPIO_DS_12 = 3, // 12mA +}; + +enum gpio_pull { + PULL_NONE = 0, + PULL_DOWN = 1, + PULL_UP = 1 +}; + +// ie: interrupt-enable (1: enable, 0: disable) +// ds: drive-strength (00: 2mA, 01: 4mA, 10: 8mA, 11: 12mA) +// pu: pull up (1: enable, 0: disable) +// pd: pull down (1: enable, 0: disable) +// slew: slew rate (0: Slow (Half frequency), 1: Fast) +// smt: Active high Schmitt trigger selector (0: No hysteresis, 1: Schmitt trigger enabled) +// pos: Power-on-Start enabler (1: Enable active pull down for loss of core power, 0: Active pull-down capability disabled) +#define GPIO_PADCFG (ie, ds, pu, pd, slew, smt, pos) \ + ((ie << GPIO_IE_SHIFT ) & GPIO_IE_MASK) | \ + ((ds << GPIO_DS_SHIFT ) & GPIO_DS_MASK) | \ + ((pu << GPIO_PU_SHIFT ) & GPIO_PU_MASK) | \ + ((pd << GPIO_PD_SHIFT ) & GPIO_PD_MASK) | \ + ((slew << GPIO_SLEW_SHIFT) & GPIO_SLEW_MASK) | \ + ((smt << GPIO_SMT_SHIFT ) & GPIO_SMT_MASK) | \ + ((pos << GPIO_POS_SHIFT ) & GPIO_POS_MASK); + +// this is to satisfy src/include/gpio.h +typedef u32 gpio_t; + +struct gpio_config { + gpio_t port; + unsigned int doen; + unsigned int dout; + // contains the GPIO pin number (+2 since GPIO0 and GPIO1 are not available) that is + // attached to a predefined input signal (e.g. the first din register contains the gpio number that is supposed to be mapped to the uart rx input signal) + unsigned int gpi; +}; + +void gpio_config_padcfg(u32 port, u32 padcfg); +void gpio_config(struct gpio_config config); + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h b/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h new file mode 100644 index 0000000..42ab06c --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/jh7110-pinfunc.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * + * copied from the starfive linux kernel + */ + +#ifndef __JH7110_PINFUNC_H__ +#define __JH7110_PINFUNC_H__ + +/* + * mux bits: + * | 31 - 24 | 23 - 16 | 15 - 10 | 9 - 8 | 7 - 0 | + * | din | dout | doen | function | gpio nr | + * + * dout: output signal + * doen: output enable signal + * din: optional input signal, 0xff = none + * function: function selector + * gpio nr: gpio number, 0 - 63 + */ +#define GPIOMUX(n, dout, doen, din) ( \ + (((din) & 0xff) << 24) | \ + (((dout) & 0xff) << 16) | \ + (((doen) & 0x3f) << 10) | \ + ((n) & 0x3f)) + +#define PINMUX(n, func) ((1 << 10) | (((func) & 0x3) << 8) | ((n) & 0xff)) + +/* sys_iomux dout */ +#define GPOUT_LOW 0 +#define GPOUT_HIGH 1 +#define GPOUT_SYS_WAVE511_UART_TX 2 +#define GPOUT_SYS_CAN0_STBY 3 +#define GPOUT_SYS_CAN0_TST_NEXT_BIT 4 +#define GPOUT_SYS_CAN0_TST_SAMPLE_POINT 5 +#define GPOUT_SYS_CAN0_TXD 6 +#define GPOUT_SYS_USB_DRIVE_VBUS 7 +#define GPOUT_SYS_QSPI_CS1 8 +#define GPOUT_SYS_SPDIF 9 +#define GPOUT_SYS_HDMI_CEC_SDA 10 +#define GPOUT_SYS_HDMI_DDC_SCL 11 +#define GPOUT_SYS_HDMI_DDC_SDA 12 +#define GPOUT_SYS_WATCHDOG 13 +#define GPOUT_SYS_I2C0_CLK 14 +#define GPOUT_SYS_I2C0_DATA 15 +#define GPOUT_SYS_SDIO0_BACK_END_POWER 16 +#define GPOUT_SYS_SDIO0_CARD_POWER_EN 17 +#define GPOUT_SYS_SDIO0_CCMD_OD_PULLUP_EN 18 +#define GPOUT_SYS_SDIO0_RST 19 +#define GPOUT_SYS_UART0_TX 20 +#define GPOUT_SYS_HIFI4_JTAG_TDO 21 +#define GPOUT_SYS_JTAG_TDO 22 +#define GPOUT_SYS_PDM_MCLK 23 +#define GPOUT_SYS_PWM_CHANNEL0 24 +#define GPOUT_SYS_PWM_CHANNEL1 25 +#define GPOUT_SYS_PWM_CHANNEL2 26 +#define GPOUT_SYS_PWM_CHANNEL3 27 +#define GPOUT_SYS_PWMDAC_LEFT 28 +#define GPOUT_SYS_PWMDAC_RIGHT 29 +#define GPOUT_SYS_SPI0_CLK 30 +#define GPOUT_SYS_SPI0_FSS 31 +#define GPOUT_SYS_SPI0_TXD 32 +#define GPOUT_SYS_GMAC_PHYCLK 33 +#define GPOUT_SYS_I2SRX_BCLK 34 +#define GPOUT_SYS_I2SRX_LRCK 35 +#define GPOUT_SYS_I2STX0_BCLK 36 +#define GPOUT_SYS_I2STX0_LRCK 37 +#define GPOUT_SYS_MCLK 38 +#define GPOUT_SYS_TDM_CLK 39 +#define GPOUT_SYS_TDM_SYNC 40 +#define GPOUT_SYS_TDM_TXD 41 +#define GPOUT_SYS_TRACE_DATA0 42 +#define GPOUT_SYS_TRACE_DATA1 43 +#define GPOUT_SYS_TRACE_DATA2 44 +#define GPOUT_SYS_TRACE_DATA3 45 +#define GPOUT_SYS_TRACE_REF 46 +#define GPOUT_SYS_CAN1_STBY 47 +#define GPOUT_SYS_CAN1_TST_NEXT_BIT 48 +#define GPOUT_SYS_CAN1_TST_SAMPLE_POINT 49 +#define GPOUT_SYS_CAN1_TXD 50 +#define GPOUT_SYS_I2C1_CLK 51 +#define GPOUT_SYS_I2C1_DATA 52 +#define GPOUT_SYS_SDIO1_BACK_END_POWER 53 +#define GPOUT_SYS_SDIO1_CARD_POWER_EN 54 +#define GPOUT_SYS_SDIO1_CLK 55 +#define GPOUT_SYS_SDIO1_CMD_OD_PULLUP_EN 56 +#define GPOUT_SYS_SDIO1_CMD 57 +#define GPOUT_SYS_SDIO1_DATA0 58 +#define GPOUT_SYS_SDIO1_DATA1 59 +#define GPOUT_SYS_SDIO1_DATA2 60 +#define GPOUT_SYS_SDIO1_DATA3 61 +#define GPOUT_SYS_SDIO1_DATA4 63 +#define GPOUT_SYS_SDIO1_DATA5 63 +#define GPOUT_SYS_SDIO1_DATA6 64 +#define GPOUT_SYS_SDIO1_DATA7 65 +#define GPOUT_SYS_SDIO1_RST 66 +#define GPOUT_SYS_UART1_RTS 67 +#define GPOUT_SYS_UART1_TX 68 +#define GPOUT_SYS_I2STX1_SDO0 69 +#define GPOUT_SYS_I2STX1_SDO1 70 +#define GPOUT_SYS_I2STX1_SDO2 71 +#define GPOUT_SYS_I2STX1_SDO3 72 +#define GPOUT_SYS_SPI1_CLK 73 +#define GPOUT_SYS_SPI1_FSS 74 +#define GPOUT_SYS_SPI1_TXD 75 +#define GPOUT_SYS_I2C2_CLK 76 +#define GPOUT_SYS_I2C2_DATA 77 +#define GPOUT_SYS_UART2_RTS 78 +#define GPOUT_SYS_UART2_TX 79 +#define GPOUT_SYS_SPI2_CLK 80 +#define GPOUT_SYS_SPI2_FSS 81 +#define GPOUT_SYS_SPI2_TXD 82 +#define GPOUT_SYS_I2C3_CLK 83 +#define GPOUT_SYS_I2C3_DATA 84 +#define GPOUT_SYS_UART3_TX 85 +#define GPOUT_SYS_SPI3_CLK 86 +#define GPOUT_SYS_SPI3_FSS 87 +#define GPOUT_SYS_SPI3_TXD 88 +#define GPOUT_SYS_I2C4_CLK 89 +#define GPOUT_SYS_I2C4_DATA 90 +#define GPOUT_SYS_UART4_RTS 91 +#define GPOUT_SYS_UART4_TX 92 +#define GPOUT_SYS_SPI4_CLK 93 +#define GPOUT_SYS_SPI4_FSS 94 +#define GPOUT_SYS_SPI4_TXD 95 +#define GPOUT_SYS_I2C5_CLK 96 +#define GPOUT_SYS_I2C5_DATA 97 +#define GPOUT_SYS_UART5_RTS 98 +#define GPOUT_SYS_UART5_TX 99 +#define GPOUT_SYS_SPI5_CLK 100 +#define GPOUT_SYS_SPI5_FSS 101 +#define GPOUT_SYS_SPI5_TXD 102 +#define GPOUT_SYS_I2C6_CLK 103 +#define GPOUT_SYS_I2C6_DATA 104 +#define GPOUT_SYS_SPI6_CLK 105 +#define GPOUT_SYS_SPI6_FSS 106 +#define GPOUT_SYS_SPI6_TXD 107 + +/* aon_iomux dout */ +#define GPOUT_AON_CLK_32K_OUT 2 +#define GPOUT_AON_PTC0_PWM4 3 +#define GPOUT_AON_PTC0_PWM5 4 +#define GPOUT_AON_PTC0_PWM6 5 +#define GPOUT_AON_PTC0_PWM7 6 +#define GPOUT_AON_CLK_GCLK0 7 +#define GPOUT_AON_CLK_GCLK1 8 +#define GPOUT_AON_CLK_GCLK2 9 + +/* sys_iomux doen */ +#define GPOEN_ENABLE 0 +#define GPOEN_DISABLE 1 +#define GPOEN_SYS_HDMI_CEC_SDA 2 +#define GPOEN_SYS_HDMI_DDC_SCL 3 +#define GPOEN_SYS_HDMI_DDC_SDA 4 +#define GPOEN_SYS_I2C0_CLK 5 +#define GPOEN_SYS_I2C0_DATA 6 +#define GPOEN_SYS_HIFI4_JTAG_TDO 7 +#define GPOEN_SYS_JTAG_TDO 8 +#define GPOEN_SYS_PWM0_CHANNEL0 9 +#define GPOEN_SYS_PWM0_CHANNEL1 10 +#define GPOEN_SYS_PWM0_CHANNEL2 11 +#define GPOEN_SYS_PWM0_CHANNEL3 12 +#define GPOEN_SYS_SPI0_NSSPCTL 13 +#define GPOEN_SYS_SPI0_NSSP 14 +#define GPOEN_SYS_TDM_SYNC 15 +#define GPOEN_SYS_TDM_TXD 16 +#define GPOEN_SYS_I2C1_CLK 17 +#define GPOEN_SYS_I2C1_DATA 18 +#define GPOEN_SYS_SDIO1_CMD 19 +#define GPOEN_SYS_SDIO1_DATA0 20 +#define GPOEN_SYS_SDIO1_DATA1 21 +#define GPOEN_SYS_SDIO1_DATA2 22 +#define GPOEN_SYS_SDIO1_DATA3 23 +#define GPOEN_SYS_SDIO1_DATA4 24 +#define GPOEN_SYS_SDIO1_DATA5 25 +#define GPOEN_SYS_SDIO1_DATA6 26 +#define GPOEN_SYS_SDIO1_DATA7 27 +#define GPOEN_SYS_SPI1_NSSPCTL 28 +#define GPOEN_SYS_SPI1_NSSP 29 +#define GPOEN_SYS_I2C2_CLK 30 +#define GPOEN_SYS_I2C2_DATA 31 +#define GPOEN_SYS_SPI2_NSSPCTL 32 +#define GPOEN_SYS_SPI2_NSSP 33 +#define GPOEN_SYS_I2C3_CLK 34 +#define GPOEN_SYS_I2C3_DATA 35 +#define GPOEN_SYS_SPI3_NSSPCTL 36 +#define GPOEN_SYS_SPI3_NSSP 37 +#define GPOEN_SYS_I2C4_CLK 38 +#define GPOEN_SYS_I2C4_DATA 39 +#define GPOEN_SYS_SPI4_NSSPCTL 40 +#define GPOEN_SYS_SPI4_NSSP 41 +#define GPOEN_SYS_I2C5_CLK 42 +#define GPOEN_SYS_I2C5_DATA 43 +#define GPOEN_SYS_SPI5_NSSPCTL 44 +#define GPOEN_SYS_SPI5_NSSP 45 +#define GPOEN_SYS_I2C6_CLK 46 +#define GPOEN_SYS_I2C6_DATA 47 +#define GPOEN_SYS_SPI6_NSSPCTL 48 +#define GPOEN_SYS_SPI6_NSSP 49 + +/* aon_iomux doen */ +#define GPOEN_AON_PTC0_OE_N_4 2 +#define GPOEN_AON_PTC0_OE_N_5 3 +#define GPOEN_AON_PTC0_OE_N_6 4 +#define GPOEN_AON_PTC0_OE_N_7 5 + +/* sys_iomux gin */ +#define GPI_NONE 255 +#define GPI_SYS_WAVE511_UART_RX 0 +#define GPI_SYS_CAN0_RXD 1 +#define GPI_SYS_USB_OVERCURRENT 2 +#define GPI_SYS_SPDIF 3 +#define GPI_SYS_JTAG_RST 4 +#define GPI_SYS_HDMI_CEC_SDA 5 +#define GPI_SYS_HDMI_DDC_SCL 6 +#define GPI_SYS_HDMI_DDC_SDA 7 +#define GPI_SYS_HDMI_HPD 8 +#define GPI_SYS_I2C0_CLK 9 +#define GPI_SYS_I2C0_DATA 10 +#define GPI_SYS_SDIO0_CD 11 +#define GPI_SYS_SDIO0_INT 12 +#define GPI_SYS_SDIO0_WP 13 +#define GPI_SYS_UART0_RX 14 +#define GPI_SYS_HIFI4_JTAG_TCK 15 +#define GPI_SYS_HIFI4_JTAG_TDI 16 +#define GPI_SYS_HIFI4_JTAG_TMS 17 +#define GPI_SYS_HIFI4_JTAG_RST 18 +#define GPI_SYS_JTAG_TDI 19 +#define GPI_SYS_JTAG_TMS 20 +#define GPI_SYS_PDM_DMIC0 21 +#define GPI_SYS_PDM_DMIC1 22 +#define GPI_SYS_I2SRX_SDIN0 23 +#define GPI_SYS_I2SRX_SDIN1 24 +#define GPI_SYS_I2SRX_SDIN2 25 +#define GPI_SYS_SPI0_CLK 26 +#define GPI_SYS_SPI0_FSS 27 +#define GPI_SYS_SPI0_RXD 28 +#define GPI_SYS_JTAG_TCK 29 +#define GPI_SYS_MCLK_EXT 30 +#define GPI_SYS_I2SRX_BCLK 31 +#define GPI_SYS_I2SRX_LRCK 32 +#define GPI_SYS_I2STX1_BCLK 33 +#define GPI_SYS_I2STX1_LRCK 34 +#define GPI_SYS_TDM_CLK 35 +#define GPI_SYS_TDM_RXD 36 +#define GPI_SYS_TDM_SYNC 37 +#define GPI_SYS_CAN1_RXD 38 +#define GPI_SYS_I2C1_CLK 39 +#define GPI_SYS_I2C1_DATA 40 +#define GPI_SYS_SDIO1_CD 41 +#define GPI_SYS_SDIO1_INT 42 +#define GPI_SYS_SDIO1_WP 43 +#define GPI_SYS_SDIO1_CMD 44 +#define GPI_SYS_SDIO1_DATA0 45 +#define GPI_SYS_SDIO1_DATA1 46 +#define GPI_SYS_SDIO1_DATA2 47 +#define GPI_SYS_SDIO1_DATA3 48 +#define GPI_SYS_SDIO1_DATA4 49 +#define GPI_SYS_SDIO1_DATA5 50 +#define GPI_SYS_SDIO1_DATA6 51 +#define GPI_SYS_SDIO1_DATA7 52 +#define GPI_SYS_SDIO1_STRB 53 +#define GPI_SYS_UART1_CTS 54 +#define GPI_SYS_UART1_RX 55 +#define GPI_SYS_SPI1_CLK 56 +#define GPI_SYS_SPI1_FSS 57 +#define GPI_SYS_SPI1_RXD 58 +#define GPI_SYS_I2C2_CLK 59 +#define GPI_SYS_I2C2_DATA 60 +#define GPI_SYS_UART2_CTS 61 +#define GPI_SYS_UART2_RX 62 +#define GPI_SYS_SPI2_CLK 63 +#define GPI_SYS_SPI2_FSS 64 +#define GPI_SYS_SPI2_RXD 65 +#define GPI_SYS_I2C3_CLK 66 +#define GPI_SYS_I2C3_DATA 67 +#define GPI_SYS_UART3_RX 68 +#define GPI_SYS_SPI3_CLK 69 +#define GPI_SYS_SPI3_FSS 70 +#define GPI_SYS_SPI3_RXD 71 +#define GPI_SYS_I2C4_CLK 72 +#define GPI_SYS_I2C4_DATA 73 +#define GPI_SYS_UART4_CTS 74 +#define GPI_SYS_UART4_RX 75 +#define GPI_SYS_SPI4_CLK 76 +#define GPI_SYS_SPI4_FSS 77 +#define GPI_SYS_SPI4_RXD 78 +#define GPI_SYS_I2C5_CLK 79 +#define GPI_SYS_I2C5_DATA 80 +#define GPI_SYS_UART5_CTS 81 +#define GPI_SYS_UART5_RX 82 +#define GPI_SYS_SPI5_CLK 83 +#define GPI_SYS_SPI5_FSS 84 +#define GPI_SYS_SPI5_RXD 85 +#define GPI_SYS_I2C6_CLK 86 +#define GPI_SYS_I2C6_DATA 87 +#define GPI_SYS_SPI6_CLK 88 +#define GPI_SYS_SPI6_FSS 89 +#define GPI_SYS_SPI6_RXD 90 + +/* aon_iomux gin */ +#define GPI_AON_PMU_GPIO_WAKEUP_0 0 +#define GPI_AON_PMU_GPIO_WAKEUP_1 1 +#define GPI_AON_PMU_GPIO_WAKEUP_2 2 +#define GPI_AON_PMU_GPIO_WAKEUP_3 3 + +#endif diff --git a/src/soc/starfive/jh7110/include/soc/jh7110.dtsi b/src/soc/starfive/jh7110/include/soc/jh7110.dtsi new file mode 100644 index 0000000..11cac5f --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/jh7110.dtsi @@ -0,0 +1,1360 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2022 StarFive Technology Co., Ltd. + * Copyright (C) 2022 Emil Renner Berthing kernel@esmil.dk + */ + +/dts-v1/; +#include <dt-bindings/clock/starfive,jh7110-crg.h> +#include <dt-bindings/power/starfive,jh7110-pmu.h> +#include <dt-bindings/reset/starfive,jh7110-crg.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + compatible = "starfive,jh7110"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + S7_0: cpu@0 { + compatible = "sifive,s7", "riscv"; + reg = <0>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <16384>; + next-level-cache = <&ccache>; + riscv,isa = "rv64imac_zba_zbb"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_1: cpu@1 { + compatible = "sifive,u74-mc", "riscv"; + reg = <1>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu1_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_2: cpu@2 { + compatible = "sifive,u74-mc", "riscv"; + reg = <2>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu2_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_3: cpu@3 { + compatible = "sifive,u74-mc", "riscv"; + reg = <3>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu3_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + U74_4: cpu@4 { + compatible = "sifive,u74-mc", "riscv"; + reg = <4>; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <40>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <40>; + mmu-type = "riscv,sv39"; + next-level-cache = <&ccache>; + riscv,isa = "rv64imafdc_zba_zbb"; + tlb-split; + operating-points-v2 = <&cpu_opp>; + clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>; + clock-names = "cpu"; + #cooling-cells = <2>; + + cpu4_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&S7_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + + core2 { + cpu = <&U74_2>; + }; + + core3 { + cpu = <&U74_3>; + }; + + core4 { + cpu = <&U74_4>; + }; + }; + }; + }; + + cpu_opp: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + opp-microvolt = <800000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <800000>; + }; + opp-750000000 { + opp-hz = /bits/ 64 <750000000>; + opp-microvolt = <800000>; + }; + opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1040000>; + }; + }; + + display: display-subsystem { + compatible = "starfive,display-subsystem"; + + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_CORE>, + <&voutcrg JH7110_VOUTCLK_DC8200_AXI>, + <&voutcrg JH7110_VOUTCLK_DC8200_AHB>; + clock-names = "noc_bus", "dc_core", "axi_core", "ahb"; + resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>, + <&voutcrg JH7110_VOUTRST_DC8200_AHB>, + <&voutcrg JH7110_VOUTRST_DC8200_CORE>; + reset-names = "axi","ahb", "core"; + }; + + dsi_encoder: dsi_encoder { + compatible = "starfive,dsi-encoder"; + starfive,syscon = <&vout_syscon 0x8 0x08>; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <15000>; + + thermal-sensors = <&sfctemp>; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = + <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + + trips { + cpu_alert0: cpu_alert0 { + /* milliCelsius */ + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit { + /* milliCelsius */ + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + + dvp_clk: dvp-clock { + compatible = "fixed-clock"; + clock-output-names = "dvp_clk"; + #clock-cells = <0>; + }; + + gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac0_rmii_refin: gmac0-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac0_rmii_refin"; + #clock-cells = <0>; + }; + + gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rgmii_rxin"; + #clock-cells = <0>; + }; + + gmac1_rmii_refin: gmac1-rmii-refin-clock { + compatible = "fixed-clock"; + clock-output-names = "gmac1_rmii_refin"; + #clock-cells = <0>; + }; + + hdmitx0_pixelclk: hdmitx0-pixel-clock { + compatible = "fixed-clock"; + clock-output-names = "hdmitx0_pixelclk"; + #clock-cells = <0>; + }; + + i2srx_bclk_ext: i2srx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_bclk_ext"; + #clock-cells = <0>; + }; + + i2srx_lrck_ext: i2srx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2srx_lrck_ext"; + #clock-cells = <0>; + }; + + i2stx_bclk_ext: i2stx-bclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_bclk_ext"; + #clock-cells = <0>; + }; + + i2stx_lrck_ext: i2stx-lrck-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "i2stx_lrck_ext"; + #clock-cells = <0>; + }; + + mclk_ext: mclk-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "mclk_ext"; + #clock-cells = <0>; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc"; + #clock-cells = <0>; + }; + + rtc_osc: rtc-oscillator { + compatible = "fixed-clock"; + clock-output-names = "rtc_osc"; + #clock-cells = <0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,lpi_en; + snps,wr_osr_lmt = <15>; + snps,rd_osr_lmt = <15>; + snps,blen = <256 128 64 32 0 0 0>; + }; + + tdm_ext: tdm-ext-clock { + compatible = "fixed-clock"; + clock-output-names = "tdm_ext"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clint: timer@2000000 { + compatible = "starfive,jh7110-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; + }; + + ccache: cache-controller@2010000 { + compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache"; + reg = <0x0 0x2010000 0x0 0x4000>; + interrupts = <1>, <3>, <4>, <2>; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + }; + + plic: interrupt-controller@c000000 { + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <0>; + riscv,ndev = <136>; + }; + + uart0: serial@10000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>, + <&syscrg JH7110_SYSCLK_UART0_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART0_APB>; + interrupts = <32>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@10010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>, + <&syscrg JH7110_SYSCLK_UART1_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART1_APB>; + interrupts = <33>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@10020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x10020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>, + <&syscrg JH7110_SYSCLK_UART2_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART2_APB>; + interrupts = <34>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c0: i2c@10030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C0_APB>; + interrupts = <35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C1_APB>; + interrupts = <36>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x10050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C2_APB>; + interrupts = <37>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@10060000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>, + <&syscrg JH7110_SYSCLK_SPI0_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI0_APB>; + interrupts = <38>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@10070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>, + <&syscrg JH7110_SYSCLK_SPI1_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI1_APB>; + interrupts = <39>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@10080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x10080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>, + <&syscrg JH7110_SYSCLK_SPI2_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI2_APB>; + interrupts = <40>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + tdm: tdm@10090000 { + compatible = "starfive,jh7110-tdm"; + reg = <0x0 0x10090000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>, + <&syscrg JH7110_SYSCLK_TDM_APB>, + <&syscrg JH7110_SYSCLK_TDM_INTERNAL>, + <&syscrg JH7110_SYSCLK_TDM_TDM>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&tdm_ext>; + clock-names = "tdm_ahb", "tdm_apb", + "tdm_internal", "tdm", + "mclk_inner", "tdm_ext"; + resets = <&syscrg JH7110_SYSRST_TDM_AHB>, + <&syscrg JH7110_SYSRST_TDM_APB>, + <&syscrg JH7110_SYSRST_TDM_CORE>; + dmas = <&dma 20>, <&dma 21>; + dma-names = "rx","tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pwmdac: pwmdac@100b0000 { + compatible = "starfive,jh7110-pwmdac"; + reg = <0x0 0x100b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>, + <&syscrg JH7110_SYSCLK_PWMDAC_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>; + dmas = <&dma 22>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2srx: i2s@100e0000 { + compatible = "starfive,jh7110-i2srx"; + reg = <0x0 0x100e0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2SRX_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2SRX_BCLK>, + <&syscrg JH7110_SYSCLK_I2SRX_LRCK>, + <&i2srx_bclk_ext>, + <&i2srx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2SRX_APB>, + <&syscrg JH7110_SYSRST_I2SRX_BCLK>; + dmas = <0>, <&dma 24>; + dma-names = "tx", "rx"; + starfive,syscon = <&sys_syscon 0x18 0x2>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + usb0: usb@10100000 { + compatible = "starfive,jh7110-usb"; + ranges = <0x0 0x0 0x10100000 0x100000>; + #address-cells = <1>; + #size-cells = <1>; + starfive,stg-syscon = <&stg_syscon 0x4>; + clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>, + <&stgcrg JH7110_STGCLK_USB0_STB>, + <&stgcrg JH7110_STGCLK_USB0_APB>, + <&stgcrg JH7110_STGCLK_USB0_AXI>, + <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>; + clock-names = "lpm", "stb", "apb", "axi", "utmi_apb"; + resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>, + <&stgcrg JH7110_STGRST_USB0_APB>, + <&stgcrg JH7110_STGRST_USB0_AXI>, + <&stgcrg JH7110_STGRST_USB0_UTMI_APB>; + reset-names = "pwrup", "apb", "axi", "utmi_apb"; + status = "disabled"; + + usb_cdns3: usb@0 { + compatible = "cdns,usb3"; + reg = <0x0 0x10000>, + <0x10000 0x10000>, + <0x20000 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <100>, <108>, <110>; + interrupt-names = "host", "peripheral", "otg"; + phys = <&usbphy0>; + phy-names = "cdns3,usb2-phy"; + }; + }; + + usbphy0: phy@10200000 { + compatible = "starfive,jh7110-usb-phy"; + reg = <0x0 0x10200000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_USB_125M>, + <&stgcrg JH7110_STGCLK_USB0_APP_125>; + clock-names = "125m", "app_125m"; + #phy-cells = <0>; + }; + + pciephy0: phy@10210000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10210000 0x0 0x10000>; + #phy-cells = <0>; + }; + + pciephy1: phy@10220000 { + compatible = "starfive,jh7110-pcie-phy"; + reg = <0x0 0x10220000 0x0 0x10000>; + #phy-cells = <0>; + }; + + stgcrg: clock-controller@10230000 { + compatible = "starfive,jh7110-stgcrg"; + reg = <0x0 0x10230000 0x0 0x10000>; + clocks = <&osc>, + <&syscrg JH7110_SYSCLK_HIFI4_CORE>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_USB_125M>, + <&syscrg JH7110_SYSCLK_CPU_BUS>, + <&syscrg JH7110_SYSCLK_HIFI4_AXI>, + <&syscrg JH7110_SYSCLK_NOCSTG_BUS>, + <&syscrg JH7110_SYSCLK_APB_BUS>; + clock-names = "osc", "hifi4_core", + "stg_axiahb", "usb_125m", + "cpu_bus", "hifi4_axi", + "nocstg_bus", "apb_bus"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + stg_syscon: syscon@10240000 { + compatible = "starfive,jh7110-stg-syscon", "syscon"; + reg = <0x0 0x10240000 0x0 0x1000>; + }; + + uart3: serial@12000000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12000000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>, + <&syscrg JH7110_SYSCLK_UART3_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART3_APB>; + interrupts = <45>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart4: serial@12010000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>, + <&syscrg JH7110_SYSCLK_UART4_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART4_APB>; + interrupts = <46>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart5: serial@12020000 { + compatible = "snps,dw-apb-uart"; + reg = <0x0 0x12020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>, + <&syscrg JH7110_SYSCLK_UART5_APB>; + clock-names = "baudclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_UART5_APB>; + interrupts = <47>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + i2c3: i2c@12030000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12030000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C3_APB>; + interrupts = <48>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@12040000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C4_APB>; + interrupts = <49>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@12050000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12050000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C5_APB>; + interrupts = <50>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@12060000 { + compatible = "snps,designware-i2c"; + reg = <0x0 0x12060000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>; + clock-names = "ref"; + resets = <&syscrg JH7110_SYSRST_I2C6_APB>; + interrupts = <51>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi3: spi@12070000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>, + <&syscrg JH7110_SYSCLK_SPI3_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI3_APB>; + interrupts = <52>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi4: spi@12080000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12080000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>, + <&syscrg JH7110_SYSCLK_SPI4_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI4_APB>; + interrupts = <53>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi5: spi@12090000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x12090000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>, + <&syscrg JH7110_SYSCLK_SPI5_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI5_APB>; + interrupts = <54>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@120a0000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0x0 0x120A0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>, + <&syscrg JH7110_SYSCLK_SPI6_APB>; + clock-names = "sspclk", "apb_pclk"; + resets = <&syscrg JH7110_SYSRST_SPI6_APB>; + interrupts = <55>; + arm,primecell-periphid = <0x00041022>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2stx0: i2s@120b0000 { + compatible = "starfive,jh7110-i2stx0"; + reg = <0x0 0x120b0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX0_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner","mclk_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX0_APB>, + <&syscrg JH7110_SYSRST_I2STX0_BCLK>; + dmas = <&dma 47>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + i2stx1: i2s@120c0000 { + compatible = "starfive,jh7110-i2stx1"; + reg = <0x0 0x120c0000 0x0 0x1000>; + clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>, + <&syscrg JH7110_SYSCLK_I2STX1_APB>, + <&syscrg JH7110_SYSCLK_MCLK>, + <&syscrg JH7110_SYSCLK_MCLK_INNER>, + <&mclk_ext>, + <&syscrg JH7110_SYSCLK_I2STX1_BCLK>, + <&syscrg JH7110_SYSCLK_I2STX1_LRCK>, + <&i2stx_bclk_ext>, + <&i2stx_lrck_ext>; + clock-names = "i2sclk", "apb", "mclk", + "mclk_inner", "mclk_ext", "bclk", + "lrck", "bclk_ext", "lrck_ext"; + resets = <&syscrg JH7110_SYSRST_I2STX1_APB>, + <&syscrg JH7110_SYSRST_I2STX1_BCLK>; + dmas = <&dma 48>; + dma-names = "tx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + pwm: pwm@120d0000 { + compatible = "starfive,jh7110-pwm", "opencores,pwm-v1"; + reg = <0x0 0x120d0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + + sfctemp: temperature-sensor@120e0000 { + compatible = "starfive,jh7110-temp"; + reg = <0x0 0x120e0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>, + <&syscrg JH7110_SYSCLK_TEMP_APB>; + clock-names = "sense", "bus"; + resets = <&syscrg JH7110_SYSRST_TEMP_CORE>, + <&syscrg JH7110_SYSRST_TEMP_APB>; + reset-names = "sense", "bus"; + #thermal-sensor-cells = <0>; + }; + + qspi: spi@13010000 { + compatible = "starfive,jh7110-qspi", "cdns,qspi-nor"; + reg = <0x0 0x13010000 0x0 0x10000>, + <0x0 0x21000000 0x0 0x400000>; + interrupts = <25>; + clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>, + <&syscrg JH7110_SYSCLK_QSPI_AHB>, + <&syscrg JH7110_SYSCLK_QSPI_APB>; + clock-names = "ref", "ahb", "apb"; + resets = <&syscrg JH7110_SYSRST_QSPI_APB>, + <&syscrg JH7110_SYSRST_QSPI_AHB>, + <&syscrg JH7110_SYSRST_QSPI_REF>; + reset-names = "qspi", "qspi-ocp", "rstc_ref"; + cdns,fifo-depth = <256>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x0>; + status = "disabled"; + }; + + syscrg: clock-controller@13020000 { + compatible = "starfive,jh7110-syscrg"; + reg = <0x0 0x13020000 0x0 0x10000>; + clocks = <&osc>, <&gmac1_rmii_refin>, + <&gmac1_rgmii_rxin>, + <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, + <&i2srx_bclk_ext>, <&i2srx_lrck_ext>, + <&tdm_ext>, <&mclk_ext>, + <&pllclk JH7110_PLLCLK_PLL0_OUT>, + <&pllclk JH7110_PLLCLK_PLL1_OUT>, + <&pllclk JH7110_PLLCLK_PLL2_OUT>; + clock-names = "osc", "gmac1_rmii_refin", + "gmac1_rgmii_rxin", + "i2stx_bclk_ext", "i2stx_lrck_ext", + "i2srx_bclk_ext", "i2srx_lrck_ext", + "tdm_ext", "mclk_ext", + "pll0_out", "pll1_out", "pll2_out"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + sys_syscon: syscon@13030000 { + compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; + reg = <0x0 0x13030000 0x0 0x1000>; + + pllclk: clock-controller { + compatible = "starfive,jh7110-pll"; + clocks = <&osc>; + #clock-cells = <1>; + }; + }; + + sysgpio: pinctrl@13040000 { + compatible = "starfive,jh7110-sys-pinctrl"; + reg = <0x0 0x13040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>; + resets = <&syscrg JH7110_SYSRST_IOMUX_APB>; + interrupts = <86>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + timer@13050000 { + compatible = "starfive,jh7110-timer"; + reg = <0x0 0x13050000 0x0 0x10000>; + interrupts = <69>, <70>, <71>, <72>; + clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>, + <&syscrg JH7110_SYSCLK_TIMER0>, + <&syscrg JH7110_SYSCLK_TIMER1>, + <&syscrg JH7110_SYSCLK_TIMER2>, + <&syscrg JH7110_SYSCLK_TIMER3>; + clock-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + resets = <&syscrg JH7110_SYSRST_TIMER_APB>, + <&syscrg JH7110_SYSRST_TIMER0>, + <&syscrg JH7110_SYSRST_TIMER1>, + <&syscrg JH7110_SYSRST_TIMER2>, + <&syscrg JH7110_SYSRST_TIMER3>; + reset-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + + watchdog@13070000 { + compatible = "starfive,jh7110-wdt"; + reg = <0x0 0x13070000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_WDT_APB>, + <&syscrg JH7110_SYSCLK_WDT_CORE>; + clock-names = "apb", "core"; + resets = <&syscrg JH7110_SYSRST_WDT_APB>, + <&syscrg JH7110_SYSRST_WDT_CORE>; + }; + + crypto: crypto@16000000 { + compatible = "starfive,jh7110-crypto"; + reg = <0x0 0x16000000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + interrupts = <28>; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + dmas = <&sdma 1 2>, <&sdma 0 2>; + dma-names = "tx", "rx"; + }; + + sdma: dma-controller@16008000 { + compatible = "arm,pl080", "arm,primecell"; + arm,primecell-periphid = <0x00041080>; + reg = <0x0 0x16008000 0x0 0x4000>; + interrupts = <29>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>; + clock-names = "apb_pclk"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + lli-bus-interface-ahb1; + mem-bus-interface-ahb1; + memcpy-burst-size = <256>; + memcpy-bus-width = <32>; + #dma-cells = <2>; + }; + + rng: rng@1600c000 { + compatible = "starfive,jh7110-trng"; + reg = <0x0 0x1600C000 0x0 0x4000>; + clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>, + <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>; + clock-names = "hclk", "ahb"; + resets = <&stgcrg JH7110_STGRST_SEC_AHB>; + interrupts = <30>; + }; + + mmc0: mmc@16010000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16010000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>, + <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>; + reset-names = "reset"; + interrupts = <74>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>; + status = "disabled"; + }; + + mmc1: mmc@16020000 { + compatible = "starfive,jh7110-mmc"; + reg = <0x0 0x16020000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>, + <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + clock-names = "biu","ciu"; + resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>; + reset-names = "reset"; + interrupts = <75>; + fifo-depth = <32>; + fifo-watermark-aligned; + data-addr = <0>; + starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>; + status = "disabled"; + }; + + gmac0: ethernet@16030000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16030000 0x0 0x10000>; + clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>, + <&aoncrg JH7110_AONCLK_GMAC0_AHB>, + <&syscrg JH7110_SYSCLK_GMAC0_PTP>, + <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>, + <&aoncrg JH7110_AONRST_GMAC0_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <7>, <6>, <5>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&aon_syscon 0xc 0x12>; + status = "disabled"; + }; + + gmac1: ethernet@16040000 { + compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20"; + reg = <0x0 0x16040000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>, + <&syscrg JH7110_SYSCLK_GMAC1_AHB>, + <&syscrg JH7110_SYSCLK_GMAC1_PTP>, + <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>, + <&syscrg JH7110_SYSCLK_GMAC1_GTXC>; + clock-names = "stmmaceth", "pclk", "ptp_ref", + "tx", "gtx"; + resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>, + <&syscrg JH7110_SYSRST_GMAC1_AHB>; + reset-names = "stmmaceth", "ahb"; + interrupts = <78>, <77>, <76>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + rx-fifo-depth = <2048>; + tx-fifo-depth = <2048>; + snps,multicast-filter-bins = <64>; + snps,perfect-filter-entries = <256>; + snps,fixed-burst; + snps,no-pbl-x8; + snps,force_thresh_dma_mode; + snps,axi-config = <&stmmac_axi_setup>; + snps,tso; + snps,en-tx-lpi-clockgating; + snps,txpbl = <16>; + snps,rxpbl = <16>; + starfive,syscon = <&sys_syscon 0x90 0x2>; + status = "disabled"; + }; + + dma: dma-controller@16050000 { + compatible = "starfive,jh7110-axi-dma"; + reg = <0x0 0x16050000 0x0 0x10000>; + clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>, + <&stgcrg JH7110_STGCLK_DMA1P_AHB>; + clock-names = "core-clk", "cfgr-clk"; + resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>, + <&stgcrg JH7110_STGRST_DMA1P_AHB>; + interrupts = <73>; + #dma-cells = <1>; + dma-channels = <4>; + snps,dma-masters = <1>; + snps,data-width = <3>; + snps,block-size = <65536 65536 65536 65536>; + snps,priority = <0 1 2 3>; + snps,axi-max-burst-len = <16>; + }; + + aoncrg: clock-controller@17000000 { + compatible = "starfive,jh7110-aoncrg"; + reg = <0x0 0x17000000 0x0 0x10000>; + clocks = <&osc>, <&gmac0_rmii_refin>, + <&gmac0_rgmii_rxin>, + <&syscrg JH7110_SYSCLK_STG_AXIAHB>, + <&syscrg JH7110_SYSCLK_APB_BUS>, + <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>, + <&rtc_osc>; + clock-names = "osc", "gmac0_rmii_refin", + "gmac0_rgmii_rxin", "stg_axiahb", + "apb_bus", "gmac0_gtxclk", + "rtc_osc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + aon_syscon: syscon@17010000 { + compatible = "starfive,jh7110-aon-syscon", "syscon"; + reg = <0x0 0x17010000 0x0 0x1000>; + #power-domain-cells = <1>; + }; + + aongpio: pinctrl@17020000 { + compatible = "starfive,jh7110-aon-pinctrl"; + reg = <0x0 0x17020000 0x0 0x10000>; + resets = <&aoncrg JH7110_AONRST_IOMUX>; + interrupts = <85>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-controller; + #gpio-cells = <2>; + }; + + pwrc: power-controller@17030000 { + compatible = "starfive,jh7110-pmu"; + reg = <0x0 0x17030000 0x0 0x10000>; + interrupts = <111>; + #power-domain-cells = <1>; + }; + + csi2rx: csi@19800000 { + compatible = "starfive,jh7110-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x19800000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_VIN_SYS>, + <&ispcrg JH7110_ISPCLK_VIN_APB>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPCLK_VIN_PIXEL_IF3>; + clock-names = "sys_clk", "p_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + resets = <&ispcrg JH7110_ISPRST_VIN_SYS>, + <&ispcrg JH7110_ISPRST_VIN_APB>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF0>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF1>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF2>, + <&ispcrg JH7110_ISPRST_VIN_PIXEL_IF3>; + reset-names = "sys", "reg_bank", + "pixel_if0", "pixel_if1", + "pixel_if2", "pixel_if3"; + phys = <&csi_phy>; + phy-names = "dphy"; + status = "disabled"; + }; + + ispcrg: clock-controller@19810000 { + compatible = "starfive,jh7110-ispcrg"; + reg = <0x0 0x19810000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>, + <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>, + <&dvp_clk>; + clock-names = "isp_top_core", "isp_top_axi", + "noc_bus_isp_axi", "dvp_clk"; + resets = <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>, + <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_ISP>; + }; + + csi_phy: phy@19820000 { + compatible = "starfive,jh7110-dphy-rx"; + reg = <0x0 0x19820000 0x0 0x10000>; + clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>, + <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>; + clock-names = "cfg", "ref", "tx"; + resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>, + <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>; + power-domains = <&aon_syscon JH7110_AON_PD_DPHY_RX>; + #phy-cells = <0>; + }; + + camss: isp@19840000 { + compatible = "starfive,jh7110-camss"; + reg = <0x0 0x19840000 0x0 0x10000>, + <0x0 0x19870000 0x0 0x30000>; + reg-names = "syscon", "isp"; + clocks = <&ispcrg JH7110_ISPCLK_DOM4_APB_FUNC>, + <&ispcrg JH7110_ISPCLK_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPCLK_DVP_INV>, + <&ispcrg JH7110_ISPCLK_VIN_P_AXI_WR>, + <&ispcrg JH7110_ISPCLK_MIPI_RX0_PXL>, + <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>, + <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>; + clock-names = "apb_func", "wrapper_clk_c", "dvp_inv", + "axiwr", "mipi_rx0_pxl", "ispcore_2x", + "isp_axi"; + resets = <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_P>, + <&ispcrg JH7110_ISPRST_ISPV2_TOP_WRAPPER_C>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_RD>, + <&ispcrg JH7110_ISPRST_VIN_P_AXI_WR>, + <&syscrg JH7110_SYSRST_ISP_TOP>, + <&syscrg JH7110_SYSRST_ISP_TOP_AXI>; + reset-names = "wrapper_p", "wrapper_c", "axird", + "axiwr", "isp_top_n", "isp_top_axi"; + power-domains = <&pwrc JH7110_PD_ISP>; + interrupts = <92>, <87>, <90>, <88>; + status = "disabled"; + }; + + dc8200: lcd-controller@29400000 { + compatible = "starfive,jh7110-dc8200"; + reg = <0x0 0x29400000 0x0 0x100>, + <0x0 0x29400800 0x0 0x2000>; + interrupts = <95>; + clocks = <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>, + <&hdmitx0_pixelclk>, + <&voutcrg JH7110_VOUTCLK_DC8200_PIX>; + clock-names = "channel0", "channel1", + "hdmi_tx", "dc_parent"; + }; + + hdmi: hdmi@29590000 { + compatible = "starfive,jh7110-inno-hdmi"; + reg = <0x0 0x29590000 0x0 0x4000>; + interrupts = <99>; + + clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>, + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>; + clock-names = "sysclk", "mclk", "bclk"; + resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>; + #sound-dai-cells = <0>; + }; + + vout_syscon: syscon@295b0000 { + compatible = "starfive,jh7110-vout-syscon", "syscon"; + reg = <0 0x295b0000 0 0x90>; + }; + + voutcrg: clock-controller@295c0000 { + compatible = "starfive,jh7110-voutcrg"; + reg = <0x0 0x295c0000 0x0 0x10000>; + clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>, + <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>, + <&syscrg JH7110_SYSCLK_I2STX0_BCLK>, + <&hdmitx0_pixelclk>; + clock-names = "vout_src", "vout_top_ahb", + "vout_top_axi", "vout_top_hdmitx0_mclk", + "i2stx0_bclk", "hdmitx0_pixelclk"; + resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + power-domains = <&pwrc JH7110_PD_VOUT>; + }; + + pcie0: pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts = <57>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; +}; diff --git a/src/soc/starfive/jh7110/include/soc/sdram.h b/src/soc/starfive/jh7110/include/soc/sdram.h new file mode 100644 index 0000000..bb9dbba --- /dev/null +++ b/src/soc/starfive/jh7110/include/soc/sdram.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_STARFIVE_JH7110_SDRAM_H__ +#define __SOC_STARFIVE_JH7110_SDRAM_H__ + +#include <stdint.h> +#include <types.h> + +void sdram_init(size_t dram_size); +size_t sdram_size(void); + +#endif diff --git a/src/soc/starfive/jh7110/memlayout.ld b/src/soc/starfive/jh7110/memlayout.ld new file mode 100644 index 0000000..39d72be --- /dev/null +++ b/src/soc/starfive/jh7110/memlayout.ld @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <soc/addressmap.h> + +#include <arch/header.ld> + +SECTIONS +{ + SRAM_START(JH7110_L2LIM) + /* The 64K size is not allocated. It's just for basic size checking. */ + BOOTBLOCK(JH7110_L2LIM, 64K) + CAR_STACK(JH7110_L2LIM + 64K, 12K) // considering each harts stack is a pagesize (4K), we can potentially have up to 16 harts regarding stack space //TODO reduce it, since fu740 doesn't even have/support 16 harts + PRERAM_CBMEM_CONSOLE(JH7110_L2LIM + 76K, 8K) + CBFS_MCACHE(JH7110_L2LIM + 84K, 8K) + FMAP_CACHE(JH7110_L2LIM + 92K, 2K) + PRERAM_CBFS_CACHE(JH7110_L2LIM + 94K, 128K) + SRAM_END(JH7110_L2LIM + 2M) + + DRAM_START(JH7110_DRAM) + OPENSBI(JH7110_DRAM, 512K) + /* The 512K size is not allocated. It's just for basic size checking. */ + RAMSTAGE(JH7110_DRAM + 512K, 512K) + MEM_STACK(JH7110_DRAM + 512K + 512K, 20K) + POSTRAM_CBFS_CACHE(JH7110_DRAM + 512K + 512K + 20K, 32M - 2M) +} diff --git a/src/soc/starfive/jh7110/sdram.c b/src/soc/starfive/jh7110/sdram.c new file mode 100644 index 0000000..b4bef3d --- /dev/null +++ b/src/soc/starfive/jh7110/sdram.c @@ -0,0 +1,2971 @@ +/* SPDX-License-Identifier: Apache-2.0 */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * Author: yanhong yanhong.wang@starfivetech.com + * + * Based on starfives u-boot fork + */ + +#ifndef _STARFIVE_SDRAM_H +#define _STARFIVE_SDRAM_H + +#include <arch/mmio.h> +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/sdram.h> +#include <stdint.h> +#include <stddef.h> +#include <delay.h> + +#define SEC_CTRL_ADDR 0x1000 +#define PHY_BASE_ADDR 0x2000 +#define PHY_AC_BASE_ADDR 0x4000 + +#define DDR_BUS_SHIFT 24 +#define DDR_BUS_MASK GENMASK(29, 24) +#define DDR_BUS_OFFSET 0xAC +#define DDR_AXI_SHIFT 31 +#define DDR_AXI_MASK BIT(31) +#define DDR_AXI_OFFSET 0xB0 + +#define DDR_BUS_OSC_DIV2 0 +#define DDR_BUS_PLL1_DIV2 1 +#define DDR_BUS_PLL1_DIV4 2 +#define DDR_BUS_PLL1_DIV8 3 +#define DDR_AXI_DISABLE 0 +#define DDR_AXI_ENABLE 1 + +#define OFFSET_SEL BIT(31) +#define REG2G BIT(30) // registers that are written if DRAM is 2G big +#define REG4G BIT(29) // registers that are written if DRAM is 4G big +#define REG8G BIT(28) // registers that are written if DRAM is 8G big +#define F_ADDSET BIT(2) +#define F_SET BIT(1) +#define F_CLRSET BIT(0) +#define REGALL (REG2G | REG4G | REG8G) +#define REGSETALL (F_SET | REGALL) +#define REGCLRSETALL (F_CLRSET | REGALL) +#define REGADDSETALL (F_ADDSET | REGALL) + +//TODO negate mask in all arrays so I can properly use clrsetbits32p +//#define DDR_REG_TRIGGER(addr, mask, value) \ +// clrsetbits32p(addr, mask, value) +#define DDR_REG_TRIGGER(addr, mask, value) \ + write32p((addr), (read32p(addr) & (mask)) | (value)) + +#define DDR_BUS_REG_SET(val) \ + clrsetbits32p(JH7110_SYS_CRG(DDR_BUS_OFFSET), \ + DDR_BUS_MASK, \ + (val << DDR_BUS_SHIFT) & DDR_BUS_MASK) + +struct ddr_reg_cfg { + u32 offset; // offset in bytes + u32 mask; + u32 val; + u32 flag; +}; + +static const struct ddr_reg_cfg ddr_csr_cfg[] = { + {0x00000000, 0x00000000, 0x00000001, REGSETALL}, + {0x00000f00, 0x00000000, 0x40001030, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000f00, 0x00000000, 0x40001030, (OFFSET_SEL | F_SET | REG2G)}, + {0x00000f04, 0x00000000, 0x00000001, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000f04, 0x00000000, 0x00800001, (OFFSET_SEL | F_SET | REG2G)}, + {0x00000f10, 0x00000000, 0x00400000, (OFFSET_SEL | REGSETALL)}, + {0x00000f14, 0x00000000, 0x043fffff, (OFFSET_SEL | REGSETALL)}, + {0x00000f18, 0x00000000, 0x00000000, (OFFSET_SEL | REGSETALL)}, + {0x00000f30, 0x00000000, 0x1f000041, (OFFSET_SEL | REGSETALL)}, + {0x00000f34, 0x00000000, 0x1f000041, (OFFSET_SEL | F_SET | REG4G | REG8G)}, + {0x00000110, 0x00000000, 0xc0000001, (OFFSET_SEL | REGSETALL)}, + {0x00000114, 0x00000000, 0xffffffff, (OFFSET_SEL | REGSETALL)}, + {0x0000010c, 0x00000000, 0x00000505, REGSETALL}, + {0x0000011c, 0x00000000, 0x00000000, REGSETALL}, + {0x00000500, 0x00000000, 0x00000201, REGSETALL}, + {0x00000514, 0x00000000, 0x00000100, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000ea8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000504, 0x00000000, 0x40000000, REGSETALL} +}; + +static const struct ddr_reg_cfg ddr_csr_cfg1[] = { + {0x00000310, 0x00000000, 0x00020000, REGSETALL}, + {0x00000310, 0x00000000, 0x00020001, REGSETALL}, + {0x00000600, 0x00000000, 0x002e0176, REGSETALL}, + {0x00000604, 0x00000000, 0x002e0176, REGSETALL}, + {0x00000608, 0x00000000, 0x001700bb, REGSETALL}, + {0x0000060c, 0x00000000, 0x000b005d, REGSETALL}, + {0x00000610, 0x00000000, 0x0005002e, REGSETALL}, + {0x00000614, 0x00000000, 0x00020017, REGSETALL}, + {0x00000618, 0x00000000, 0x00020017, REGSETALL}, + {0x0000061c, 0x00000000, 0x00020017, REGSETALL}, + {0x00000678, 0x00000000, 0x00000019, REGSETALL}, + {0x00000100, 0x00000000, 0x000000f8, REGSETALL}, + {0x00000620, 0x00000000, 0x03030404, REGSETALL}, + {0x00000624, 0x00000000, 0x04030505, REGSETALL}, + {0x00000628, 0x00000000, 0x07030884, REGSETALL}, + {0x0000062c, 0x00000000, 0x13150401, REGSETALL}, + {0x00000630, 0x00000000, 0x17150604, REGSETALL}, + {0x00000634, 0x00000000, 0x00110000, REGSETALL}, + {0x00000638, 0x00000000, 0x200a0a08, REGSETALL}, + {0x0000063c, 0x00000000, 0x1730f803, REGSETALL}, + {0x00000640, 0x00000000, 0x000a0c00, REGSETALL}, + {0x00000644, 0x00000000, 0xa005000a, REGSETALL}, + {0x00000648, 0x00000000, 0x00000000, REGSETALL}, + {0x0000064c, 0x00000000, 0x00081306, REGSETALL}, + {0x00000650, 0x00000000, 0x04070304, REGSETALL}, + {0x00000654, 0x00000000, 0x00000404, REGSETALL}, + {0x00000658, 0x00000000, 0x00000060, REGSETALL}, + {0x0000065c, 0x00000000, 0x00030008, REGSETALL}, + {0x00000660, 0x00000000, 0x00000000, REGSETALL}, + {0x00000680, 0x00000000, 0x00000603, REGSETALL}, + {0x00000684, 0x00000000, 0x01000202, REGSETALL}, + {0x00000688, 0x00000000, 0x0413040d, REGSETALL}, + {0x0000068c, 0x00000000, 0x20002420, REGSETALL}, + {0x00000690, 0x00000000, 0x00140000, REGSETALL}, + {0x0000069c, 0x00000000, 0x01240074, REGSETALL}, + {0x000006a0, 0x00000000, 0x00000000, REGSETALL}, + {0x000006a4, 0x00000000, 0x20240c00, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000004, 0x00000000, 0x30010006, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010006, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30020000, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10020000, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10030031, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x300b0033, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x100b0033, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10160016, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000010, 0x00000000, 0x00000010, REGSETALL}, + {0x00000014, 0x00000000, 0x00000001, REGSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg2[] = { + {0xb8, 0xf0ffffff, 0x3000000, REGCLRSETALL}, + {0x84, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb4, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x300, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x100, REGCLRSETALL}, + {0xb8, 0xFFF0FFFF, 0x30000, REGCLRSETALL}, + {0x84, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0xac, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0xb0, 0xffffffff, 0x1, REGCLRSETALL}, + {0x248, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x3, REGCLRSETALL}, + {0x24c, 0xffffffff, 0x30000, REGCLRSETALL}, + {0x250, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x254, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0x258, 0xffffffff, 0x3000000, REGCLRSETALL}, + {0xac, 0xffffffff, 0x100, REGCLRSETALL}, + {0x10c, 0xFFFFF0FF, 0x300, REGCLRSETALL}, + {0x110, 0xFFFFFEFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFFFEFFFF, 0x0, REGCLRSETALL}, + {0x11c, 0xFEFFFFFF, 0x0, REGCLRSETALL}, + {0x120, 0xffffffff, 0x100, REGCLRSETALL}, + {0x2d0, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2dc, 0xffffffff, 0x300, REGCLRSETALL}, + {0x2e8, 0xffffffff, 0x300, REGCLRSETALL}, +}; + +static const struct ddr_reg_cfg ddr_csr_cfg3[] = { + {0x00000100, 0x00000000, 0x000000e0, REGSETALL}, + {0x00000620, 0x00000000, 0x04041417, REGSETALL}, + {0x00000624, 0x00000000, 0x09110609, REGSETALL}, + {0x00000628, 0x00000000, 0x442d0994, REGSETALL}, + {0x0000062c, 0x00000000, 0x271e102b, REGSETALL}, + {0x00000630, 0x00000000, 0x291b140a, REGSETALL}, + {0x00000634, 0x00000000, 0x001c0000, REGSETALL}, + {0x00000638, 0x00000000, 0x200f0f08, REGSETALL}, + {0x0000063c, 0x00000000, 0x29420a06, REGSETALL}, + {0x00000640, 0x00000000, 0x019e1fc1, REGSETALL}, + {0x00000644, 0x00000000, 0x10cb0196, REGSETALL}, + {0x00000648, 0x00000000, 0x00000000, REGSETALL}, + {0x0000064c, 0x00000000, 0x00082714, REGSETALL}, + {0x00000650, 0x00000000, 0x16442f0d, REGSETALL}, + {0x00000654, 0x00000000, 0x00001916, REGSETALL}, + {0x00000658, 0x00000000, 0x00000060, REGSETALL}, + {0x0000065c, 0x00000000, 0x00600020, REGSETALL}, + {0x00000660, 0x00000000, 0x00000000, REGSETALL}, + {0x00000680, 0x00000000, 0x0c00040f, REGSETALL}, + {0x00000684, 0x00000000, 0x03000604, REGSETALL}, + {0x00000688, 0x00000000, 0x0515040d, REGSETALL}, + {0x0000068c, 0x00000000, 0x20002c20, REGSETALL}, + {0x00000690, 0x00000000, 0x00140000, REGSETALL}, + {0x0000069c, 0x00000000, 0x01240074, REGSETALL}, + {0x000006a0, 0x00000000, 0x00000000, REGSETALL}, + {0x000006a4, 0x00000000, 0x202c0c00, REGSETALL}, + {0x000006a8, 0x00000000, 0x00040000, REGSETALL}, + {0x00000004, 0x00000000, 0x30010036, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010036, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x3002001b, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10010036, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30030031, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10030031, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x300b0066, (F_SET | REG4G)}, + {0x00000004, 0x00000000, 0x300b0036, (F_SET | REG8G)}, + {0x00000004, 0x00000000, 0x100b0066, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000004, 0x00000000, 0x30160016, (F_SET | REG4G | REG8G)}, + {0x00000004, 0x00000000, 0x10160016, (F_SET | REG2G)}, + {0x0000000c, 0x00000000, 0x00000002, REGSETALL}, + {0x00000410, 0x00000000, 0x00101010, REGSETALL}, + {0x00000420, 0x00000000, 0x0c181006, REGSETALL}, + {0x00000424, 0x00000000, 0x20200820, REGSETALL}, + {0x00000428, 0x00000000, 0x80000020, REGSETALL}, + {0x00000000, 0x00000000, 0x00000001, REGSETALL}, + {0x00000108, 0x00000000, 0x00003000, REGSETALL}, + {0x00000704, 0x00000000, 0x00000007, REGSETALL | OFFSET_SEL}, + {0x00000330, 0x00000000, 0x09313fff, (F_SET | REG4G | REG8G)}, + {0x00000330, 0x00000000, 0x09311fff, (F_SET | REG2G)}, + {0x00000508, 0x00000000, 0x00000033, (F_SET | REG4G | REG8G)}, + {0x00000508, 0x00000000, 0x00000013, (F_SET | REG2G)}, + {0x00000324, 0x00000000, 0x00002000, REGSETALL}, + {0x00000104, 0x00000000, 0x90000000, REGSETALL}, + {0x00000510, 0x00000000, 0x00000100, REGSETALL}, + {0x00000514, 0x00000000, 0x00000000, REGSETALL}, + {0x00000700, 0x00000000, 0x00000003, REGSETALL | OFFSET_SEL}, + {0x00000514, 0x00000000, 0x00000600, REGSETALL}, + {0x00000020, 0x00000000, 0x00000001, REGSETALL}, +}; + +static void ddr_csr_set(uintptr_t csrreg, uintptr_t secreg, const struct ddr_reg_cfg *data, + size_t len, u32 mask) +{ + for (size_t i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + uintptr_t addr; + if (data[i].flag & OFFSET_SEL) + addr = secreg + data[i].offset; + else + addr = csrreg + data[i].offset; + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else + write32p(addr, data[i].val); + } +} + +static void ddrcsr_boot(uintptr_t csrreg, uintptr_t secreg, uintptr_t phyreg, size_t size) +{ + u32 mask; + + switch (size) { + case 2UL*GiB: + mask = REG2G; + break; + case 4UL*GiB: + mask = REG4G; + break; + case 8UL*GiB: + mask = REG8G; + break; + default: + return; + }; + + size_t len = ARRAY_SIZE(ddr_csr_cfg); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg, len, mask); + + while (!(read32p(csrreg + 0x504) & BIT(31))) + ; + + write32p(csrreg + 0x504, 0x0); + write32p(csrreg + 0x50c, 0x0); + udelay(300); + write32p(csrreg + 0x50c, 0x1); + mdelay(3); + + switch (size) { + case 2UL*GiB: + write32p(csrreg + 0x10, 0x1c); + break; + case 4UL*GiB: + case 8UL*GiB: + write32p(csrreg + 0x10, 0x3c); + break; + default: + break; + }; + + write32p(csrreg + 0x14, 0x1); + udelay(4); + + len = ARRAY_SIZE(ddr_csr_cfg1); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg1, len, mask); + + udelay(4); + write32p(csrreg + 0x10, 0x11); + write32p(csrreg + 0x14, 0x1); + + switch (size) { + case 4UL*GiB: + case 8UL*GiB: + write32p(csrreg + 0x10, 0x20); + write32p(csrreg + 0x14, 0x1); + udelay(4); + write32p(csrreg + 0x10, 0x21); + write32p(csrreg + 0x14, 0x1); + break; + case 2UL*GiB: + default: + break; + }; + + write32p(csrreg + 0x514, 0x0); + while (!(read32p(csrreg + 0x518) & BIT(1))) + ; + + u32 val = read32p(csrreg + 0x518); + while ((val & 0x2) != 0x0) { + val = read32p(phyreg + 0x4); + + if ((val & 0x20) == 0x20) { + switch (val & 0x1f) { + case 0: /* ddrc_clock=12M */ + DDR_BUS_REG_SET(DDR_BUS_OSC_DIV2); + break; + case 1: /* ddrc_clock=200M */ + DDR_BUS_REG_SET(DDR_BUS_PLL1_DIV8); + break; + case 2: /* ddrc_clock=800M */ + DDR_BUS_REG_SET(DDR_BUS_PLL1_DIV2); + break; + default: + break; + }; + + write32p(phyreg + 0x8, 0x1); + while (read32p(phyreg + 0x8) & BIT(0)) + ; + } + + udelay(1); + val = read32p(csrreg + 0x518); + }; + + val = read32p(phyreg + 0x2000 + 0x14C); + val = read32p(phyreg + 0x2000 + 0x150); + write32p(phyreg + 0x2000 + 0x150, val & 0xF8000000); + + len = ARRAY_SIZE(ddr_csr_cfg2); + ddr_csr_set(phyreg + PHY_BASE_ADDR, secreg, ddr_csr_cfg2, len, mask); + + len = ARRAY_SIZE(ddr_csr_cfg3); + ddr_csr_set(csrreg, secreg, ddr_csr_cfg3, len, mask); +} + +static const u32 ddr_phy_data[] = { + 0x4f0, + 0x0, + 0x1030200, + 0x0, + 0x0, + 0x3000000, + 0x1000001, + 0x3000400, + 0x1000001, + 0x0, + 0x0, + 0x1000001, + 0x0, + 0xc00004, + 0xcc0008, + 0x660601, + 0x3, + 0x0, + 0x1, + 0xaaaa, + 0x5555, + 0xb5b5, + 0x4a4a, + 0x5656, + 0xa9a9, + 0xa9a9, + 0xb5b5, + 0x0, + 0x0, + 0x8000000, + 0x4000008, + 0x408, + 0xe4e400, + 0x71020, + 0xc0020, + 0x620, + 0x100, + 0x55555555, + 0xaaaaaaaa, + 0x55555555, + 0xaaaaaaaa, + 0x5555, + 0x1000100, + 0x800180, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x4, + 0x20, + 0x0, + 0x0, + 0x0, + 0x0, + 0x7ff0000, + 0x20008008, + 0x810, + 0x40100, + 0x0, + 0x1880c01, + 0x2003880c, + 0x20000125, + 0x7ff0200, + 0x101, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x20000, + 0x51515052, + 0x31c06000, + 0x11f0004, + 0xc0c001, + 0x3000000, + 0x30202, + 0x42100010, + 0x10c053e, + 0xf0c20, + 0x1000140, + 0xa30120, + 0xc00, + 0x210, + 0x200, + 0x2800000, + 0x80800101, + 0x3, + 0x76543210, + 0x8, + 0x2800280, + 0x2800280, + 0x2800280, + 0x2800280, + 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0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x100, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x50000, + 0x4000000, + 0x55, + 0x0, + 0x0, + 0x0, + 0xf0001, + 0x280040, + 0x5002, + 0x10101, + 0x8008, + 0x81020, + 0x0, + 0x0, + 0x1000000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x0, + 0x1010000, + 0x2020101, + 0x4040202, + 0x8080404, + 0xf0f0808, + 0xf0f0f0f, + 0x20200f0f, + 0x1b428000, + 0x4, + 0x1010000, + 0x1070501, + 0x54, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x4410, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x64, + 0x0, + 0x108, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x3000000, + 0x0, + 0x0, + 0x0, + 0x4102035, + 0x41020, + 0x1c98c98, + 0x3f400000, + 0x3f3f1f3f, + 0x1f3f3f1f, + 0x1f3f3f, + 0x0, + 0x0, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x76543210, + 0x6010198, + 0x0, + 0x0, + 0x0, + 0x40700, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x2, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1142, + 0x3020100, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x3000300, + 0x300, + 0x300, + 0x300, + 0x300, + 0x2, + 0x4011, + 0x4011, + 0x40, + 0x40, + 0x4011, + 0x1fff00, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x4011, + 0x1004011, + 0x200400, + +}; + +static void ddr_phy_util(uintptr_t phyreg) +{ + for (u32 i = 1792; i < ARRAY_SIZE(ddr_phy_data); i++) + write32p(phyreg + i * 4, ddr_phy_data[i]); + + for (u32 i = 0; i < 1792; i++) + write32p(phyreg + i * 4, ddr_phy_data[i]); +} + +static const u32 ddr_train_data[] = { + 0xb00, + 0x101, + 0x640000, + 0x1, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1, + 0x7, + 0x10002, + 0x300080f, + 0x1, + 0x5, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x1010000, + 0x280a0000, + 0x0, + 0x1, + 0x3200000f, + 0x0, + 0x0, + 0x10102, + 0x1, + 0x0, + 0x0, + 0x0, + 0xaa, + 0x55, + 0xb5, + 0x4a, + 0x56, + 0xa9, + 0xa9, + 0xb5, + 0x1000000, + 0x1000000, + 0x0, + 0xf0f0000, + 0x14, + 0x7d0, + 0x300, + 0x0, + 0x0, + 0x1000000, + 0x10101, + 0x0, + 0x30000, + 0x100, + 0x170f, + 0x0, + 0x0, + 0x0, + 0xa140a01, + 0x204010a, + 0x2080510, + 0x40400, + 0x1000101, + 0x10100, + 0x2040f00, + 0x34000000, + 0x0, + 0x0, + 0x1000000, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10100, + 0x80101, + 0x2000200, + 0x1000100, + 0x1000000, + 0x2000200, + 0x200, + 0x0, + 0x0, + 0x0, + 0xe000004, + 0xc0d100f, + 0xa09080b, + 0x2010000, + 0x80103, + 0x200, + 0x0, + 0xf000000, + 0x4, + 0xa, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x30100, + 0x1010001, + 0x10200, + 0x4000103, + 0x1050001, + 0x10600, + 0x107, + 0x0, + 0x0, + 0x10001, + 0x0, + 0x0, + 0x0, + 0x0, + 0x10000, + 0x4, + 0x0, + 0x10000, + 0x0, + 0x3c0003, + 0x80100a0, + 0x16, + 0x2c, + 0x33, + 0x20043, + 0x2000200, + 0x4, + 0x60c, + 0xa1400, + 0x280000, + 0x6, + 0x46, + 0x70, + 0x610, + 0x12b, + 0x4001035, + 0x1010404, + 0x1e01, + 0x1e001e, + 0x1000100, + 0x100, + 0x0, + 0x5060403, + 0x1011108, + 0x1010101, + 0xf0a0a, + 0x0, + 0x0, + 0x4000000, + 0x4021008, + 0x4020206, + 0xc0034, + 0x100038, + 0x17003f, + 0x10001, + 0x10001, + 0x10005, + 0x20064, + 0x100010b, + 0x60006, + 0x650100, + 0x1000065, + 0x10c010c, + 0x1e1a1e1a, + 0x1011e1a, + 0xa070601, + 0xa07060d, + 0x100b080d, + 0xc00f, + 0xc01000, + 0xc01000, + 0x21000, + 0x120005, + 0x190064, + 0x10b, + 0x1100, + 0x1e1a0056, + 0x6000101, + 0x130204, + 0x1e1a0058, + 0x1000101, + 0x230408, + 0x1e1a005e, + 0x9000101, + 0x610, + 0x4040800, + 0x40100, + 0x3000277, + 0xa032001, + 0xa0a, + 0x80908, + 0x901, + 0x1100315c, + 0xa062002, + 0xa0a, + 0x141708, + 0x150d, + 0x2d00838e, + 0xf102004, + 0xf0b, + 0x8c, + 0x578, + 0xc20, + 0x7940, + 0x206a, + 0x14424, + 0x730006, + 0x3030133, + 0x4, + 0x0, + 0x4, + 0x1, + 0x5, + 0x2, + 0x6, + 0x50, + 0x1, + 0x5, + 0x28, + 0x73, + 0xd6, + 0x1, + 0x5, + 0x6b, + 0x1000133, + 0x140040, + 0x10001, + 0x1900040, + 0x1000c, + 0x42b0040, + 0x320, + 0x360014, + 0x1010101, + 0x2020101, + 0x8080404, + 0x67676767, + 0x67676767, + 0x67676767, + 0x67676767, + 0x0, + 0x0, + 0x0, + 0x0, + 0x0, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x5500, + 0x5a00, + 0x55003c, + 0x0, + 0x3c00005a, + 0x18171615, + 0x14131211, + 0x7060504, + 0x3020100, + 0x0, + 0x0, + 0x0, + 0x1000000, + 0x4020201, + 0x80804, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x4, + 0x0, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x14, + 0x9, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, + 0x0, + 0x34, + 0x1b, + 0x31, + 0x31, + 0x0, + 0x0, + 0x4d4d, +}; + +static void ddr_phy_train(uintptr_t phyreg) +{ + for (u32 i = 0; i < ARRAY_SIZE(ddr_train_data); i++) + write32p(phyreg + i * 4, ddr_train_data[i]); +} + +static const struct ddr_reg_cfg ddr_start_cfg[] = { + {0x00000164, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000138, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000564, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000538, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000964, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000938, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d64, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d38, 0xfffffcff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffffeff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffcffff, 0x00000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x000001f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000198, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000001a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000170, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000178, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000180, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000164, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x000005f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000598, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000005a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000570, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000578, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000580, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000564, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x000009f4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000998, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x000009a4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000970, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000978, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000980, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000964, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000df4, 0xfff0ffff, 0x00010000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d98, 0xfffffffc, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000da4, 0xffffffe0, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d70, 0xfffffffe, 0x00000001, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d78, 0xffffe0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d80, 0xfffff0ff, 0x00000400, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d64, 0xffffff00, 0x00000051, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d9c, 0xffffe000, 0x00001342, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cac, 0xfffff0ff, 0x00000200, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c04, 0xfffffeff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x000000f8, 0xfffffeff, 0x00000000, REGCLRSETALL}, + {0x00000108, 0xfffffeff, 0x00000000, REGCLRSETALL}, + {0x00000298, 0xffffff80, 0x00000001, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0xffff80ff, 0x00000100, REGCLRSETALL}, + {0x000002cc, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002cc, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x00000298, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x000002d8, 0xff80ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002d8, 0x80ffffff, 0x01000000, REGCLRSETALL}, + {0x0000029c, 0xffffff80, 0x00000017, REGCLRSETALL}, + {0x000000f8, 0xfff0ffff, 0x00010000, REGCLRSETALL}, + {0x000000f8, 0xf0ffffff, 0x01000000, REGCLRSETALL}, + {0x0000029c, 0xffff80ff, 0x00001700, REGCLRSETALL}, + {0x000002e4, 0xff80ffff, 0x00200000, REGCLRSETALL}, + {0x0000010c, 0xffe0ffff, 0x00010000, REGCLRSETALL}, + {0x0000010c, 0xe0ffffff, 0x01000000, REGCLRSETALL}, + {0x000002e4, 0x80ffffff, 0x20000000, REGCLRSETALL}, + {0x00000028, 0xffffffe0, 0x00000002, REGCLRSETALL}, + {0x00000000, 0xfffffffe, 0x00000001, REGCLRSETALL}, + {0x0000002c, 0xfffffff0, 0x00000005, (F_CLRSET | REG2G)}, + {0x000003dc, 0xffffffff, 0x00000008, REGCLRSETALL}, + {0x000003e4, 0xffffffff, 0x00000800, REGCLRSETALL}, + {0x000003f0, 0xffffffff, 0x00000008, REGCLRSETALL}, + {0x000003f8, 0xffffffff, 0x00000800, REGCLRSETALL}, + {0x00000464, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x000004c4, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000524, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000584, 0xffffffff, 0x33000000, REGCLRSETALL}, + {0x00000484, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x000004e4, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x00000544, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x000005a4, 0xffffffff, 0x36000000, (F_CLRSET | REG8G)}, + {0x00000484, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x000004e4, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x00000544, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x000005a4, 0xffffffff, 0x66000000, (F_CLRSET | REG2G | REG4G)}, + {0x00000468, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000004c8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000528, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000588, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000488, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000004e8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000548, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x000005a8, 0xffffffff, 0x00160000, REGCLRSETALL}, + {0x00000468, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000004c8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000528, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000588, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000488, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000004e8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000548, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x000005a8, 0xffffff00, 0x00000017, REGCLRSETALL}, + {0x00000468, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000004c8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000528, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000588, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000488, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000004e8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000548, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x000005a8, 0xffff00ff, 0x00002000, REGCLRSETALL}, + {0x00000104, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000504, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000904, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d04, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000180, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000580, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000980, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000d80, 0x00000000, 0x00000300, (OFFSET_SEL | REGADDSETALL)}, + {0x00000180, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000580, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000980, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d80, 0xff00ffff, 0x00120000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000084, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000484, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000884, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c84, 0xffffff00, 0x00000040, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001038, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001438, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001838, 0xfcffffff, 0x03000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000014c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000054c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000094c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d4c, 0xffc0ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001098, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001498, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001898, 0xf800ffff, 0x00070000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d90, 0xfffc0000, 0x00015547, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001d94, 0xfffc0000, 0x00000007, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cf0, 0xffffe000, 0x0000007a, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001cf4, 0xffffffff, 0x00000100, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c78, 0xffffffff, 0x000000ff, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001da0, 0xfffffc00, 0x000003d5, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000016c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000056c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000096c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d6c, 0xfc00ffff, 0x03d50000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001de0, 0x00000000, 0x0cc3bfc7, (OFFSET_SEL | REGSETALL)}, + {0x00001de4, 0x00000000, 0x0000ff8f, (OFFSET_SEL | REGSETALL)}, + {0x00001de8, 0x00000000, 0x033f07ff, (OFFSET_SEL | REGSETALL)}, + {0x00001dec, 0x00000000, 0x0c3c37ff, (OFFSET_SEL | REGSETALL)}, + {0x00001df0, 0x00000000, 0x1fffff10, (OFFSET_SEL | REGSETALL)}, + {0x00001df4, 0x00000000, 0x00230070, (OFFSET_SEL | REGSETALL)}, + {0x00001df8, 0x00000000, 0x3ff7ffff, (OFFSET_SEL | REG4G | REG2G | F_SET)}, + {0x00001df8, 0x00000000, 0x3ff7ffff, (OFFSET_SEL | REG8G | F_SET)}, + {0x00001dfc, 0x00000000, 0x00000e10, (OFFSET_SEL | REGSETALL)}, + {0x00001e00, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e04, 0x00000000, 0x00188411, (OFFSET_SEL | REGSETALL)}, + {0x00001e08, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e0c, 0x00000000, 0x00180400, (OFFSET_SEL | REGSETALL)}, + {0x00001e10, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e14, 0x00000000, 0x00180400, (OFFSET_SEL | REGSETALL)}, + {0x00001e18, 0x00000000, 0x1fffffcf, (OFFSET_SEL | REGSETALL)}, + {0x00001e1c, 0x00000000, 0x00188400, (OFFSET_SEL | REGSETALL)}, + {0x00001e20, 0x00000000, 0x1fffffff, (OFFSET_SEL | REGSETALL)}, + {0x00001e24, 0x00000000, 0x04188411, (OFFSET_SEL | REGSETALL)}, + {0x00001cb4, 0x00000000, 0x00024410, (OFFSET_SEL | REGSETALL)}, + {0x00001cc0, 0x00000000, 0x00024410, (OFFSET_SEL | REGSETALL)}, + {0x00001cc8, 0x00000000, 0x0002ffff, (OFFSET_SEL | REGSETALL)}, + {0x00000130, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000530, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000930, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d30, 0xff0000f8, 0x00ff8f07, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000134, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000534, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000934, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000d34, 0xffff0000, 0x0000ff8f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001098, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001498, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001898, 0xffffff00, 0x000000ff, (OFFSET_SEL | REG4G | REG2G | F_CLRSET)}, + {0x00001098, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001498, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001898, 0xffffff00, 0x000000fb, (OFFSET_SEL | REG8G | F_CLRSET)}, + {0x00001010, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001410, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001810, 0xffffffff, 0x01000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001ce0, 0x00000000, 0x03cf07f8, (OFFSET_SEL | REGSETALL)}, + {0x00001ce4, 0x00000000, 0x0000003f, (OFFSET_SEL | REGSETALL)}, + {0x00001ce8, 0x00000000, 0x001fffff, (OFFSET_SEL | REGSETALL)}, + {0x00001cec, 0x00000000, 0x00060000, (OFFSET_SEL | REGSETALL)}, + {0x00000208, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000608, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000a08, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000e08, 0x0000ffff, 0xffff0000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000020c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000060c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000a0c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000e0c, 0xfffffff0, 0x0000000f, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000074, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000474, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000874, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c74, 0xc0ffffff, 0x10000000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000078, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000478, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000878, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c78, 0xffffffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000007c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000047c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x0000087c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x00000c7c, 0xffffffc0, 0x00000010, (OFFSET_SEL | REGCLRSETALL)}, + {0x000010bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x000014bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x000018bc, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001c40, 0xfffffff0, 0x00000008, (OFFSET_SEL | REGCLRSETALL)}, + {0x00001da0, 0xfff0ffff, 0x00080000, (OFFSET_SEL | REGCLRSETALL)}, +}; + +static void ddr_reg_set(uintptr_t reg, const struct ddr_reg_cfg *data, size_t len, u32 mask) +{ + for (size_t i = 0; i < len; i++) { + if (!(data[i].flag & mask)) + continue; + + uintptr_t addr; + if (data[i].flag & OFFSET_SEL) + addr = reg + PHY_AC_BASE_ADDR + data[i].offset; + else + addr = reg + PHY_BASE_ADDR + data[i].offset; + + if (data[i].flag & F_CLRSET) + DDR_REG_TRIGGER(addr, data[i].mask, data[i].val); + else if (data[i].flag & F_SET) + write32p(addr, data[i].val); + else + write32p(addr, read32p(addr) + data[i].val); + } +} + +static void ddr_phy_start(uintptr_t phyreg, size_t size) +{ + switch (size) { + case 2UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG2G); + break; + case 4UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG4G); + break; + case 8UL*GiB: + ddr_reg_set(phyreg, ddr_start_cfg, ARRAY_SIZE(ddr_start_cfg), REG8G); + break; + default: + die("unsupported DDR size\n"); + }; + + write32p(phyreg, 0x01); +} + +void sdram_init(size_t dram_size) +{ + printk(BIOS_DEBUG, "Initialize LPDDR4 memory\n"); + +#define JH7110_DDR_CTRL 0x15700000 +#define JH7110_DDR_PHY 0x13000000 + ddr_phy_train(JH7110_DDR_PHY + PHY_BASE_ADDR); + ddr_phy_util(JH7110_DDR_PHY + PHY_AC_BASE_ADDR); + ddr_phy_start(JH7110_DDR_PHY, 8UL*GiB); + + DDR_BUS_REG_SET(DDR_BUS_OSC_DIV2); + ddrcsr_boot(JH7110_DDR_CTRL, JH7110_DDR_CTRL + SEC_CTRL_ADDR, JH7110_DDR_PHY, dram_size); +} + +// sdram_init MUST be called before sdram_size +size_t sdram_size(void) +{ + //u64 devicepmp0 = read64((u64 *)FU740_PHYSICAL_FILTER); + //return ((devicepmp0 & 0xFFFFFFFFFFFFFF) << 2) - FU740_DRAM; + + return 8UL*GiB; //TODO get from register to account for all visionfive2 variations (e.g. 4 GB) +} + +#endif diff --git a/src/soc/starfive/jh7110/uart.c b/src/soc/starfive/jh7110/uart.c new file mode 100644 index 0000000..434c7d8 --- /dev/null +++ b/src/soc/starfive/jh7110/uart.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <console/uart.h> +#include <commonlib/bsd/helpers.h> +#include <soc/addressmap.h> +#include <soc/clock.h> + +uintptr_t uart_platform_base(unsigned int idx) +{ + if (idx < 2) + return JH7110_UART(idx); + else + return 0; +} + +unsigned int uart_platform_refclk(void) +{ + // peripheral clock is attached to UART subsystem + //return clock_get_pclk(); + return 24 * MHz; //TODO +}