Michael Büchler has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73087 )
Change subject: mb/intel/dq67sw: Add LGA1155 microATX mainboard ......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
Thank you again for making this port, and also for [uploading the logs to the board status repositor […]
My pleasure, I'm happy that it got reviewed and merged! Thanks for having a look into the logs.
1. I tried the other two options ("LZ4" and "none") and they do have an effect on the size of 'fallback/payload` in the CBFS - the compressed options make them much smaller than without compression:
``` none: fallback/payload 0x448c0 simple elf 5832760 none LZMA: fallback/payload 0x448c0 simple elf 780146 none LZ4: fallback/payload 0x448c0 simple elf 1203966 none ```
When I extract it with e.g. `build/cbfstool build/coreboot.rom extract -n fallback/payload -f payload.lzma -m x86` then it always appears at the full size of 5840896. It seems that `cbfstool` is hiding something from us!
2. I think the correct way would be to add this to the Kconfig in a new patch?
``` config PRERAM_CBMEM_CONSOLE_SIZE hex default 0x4000 ```
I tried this successfully for the ASRock H77 Pro4-M, in a local build. 0x1000 was not enough. I then checked the number of bytes in `cbmem -c1` in the lines before it says "ramstage starting":
``` $ head -n 231 4_cbmem_c1.log | wc -c 9400 ```
So it seems 0x4000 is not unreasonably large, if my "calculation" is correct. It was with all four DIMM slots populated, and with the RW_MRC_CACHE empty so it did a full initialization.
3. Here I am a bit lost. If these bus addresses correlate directly with devicetree.cb entries then these should be off as per the default setting in `src/northbridge/intel/sandybridge/chipset.cb`. But I don't really understand what these warnings mean.