[coreboot-gerrit] Change in coreboot[master]: haswell: Add Intel TXT support in romstage

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46608 )

Change subject: haswell: Add Intel TXT support in romstage
......................................................................

Patch Set 5:

I was working on it for ivybridge, but unline haswell and later platforms it requires manual APs setup before calling GETSEC. There is much assembly code to configure MTRRs, clean MCEs and rendezvous the APs right before the GETSEC call. Based on all the TXT patches I saw on gerrit, we do not do it for APs anywhere. If I am not mistaken it is related to the FIT table and loading ACM before reset vector?