Attention is currently required from: Furquan Shaikh, Karthik Ramasubramanian, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56818 )
Change subject: soc/amd/common/block/spi: Don't update spi speed if EFS is changed ......................................................................
Patch Set 2:
(1 comment)
File src/soc/amd/common/block/spi/fch_spi.c:
https://review.coreboot.org/c/coreboot/+/56818/comment/5133f80b_f63a1807 PS2, Line 84: if (CONFIG(EM100)) : fch_spi_config_em100_modes(); : else : fch_spi_config_mb_modes();
ah, that's what you meant
I think we're all in agreement that the EFS should be the basis for the speed and mode setting. That was something that I'd talked to felix about a few weeks back so that we could get rid of the structure in devicetree. (Or alternatively we update the sconfig code to create a separate header file and makefile-includable file which would allow us to use devicetree to set Makefile & pre-compiler values).
Here's where I think we go from here: - Move 3 other 3 SPI speeds into Kconfig. - Add the code to use those 3 values instead of getting the values from devicetree. - Felix wanted to make sure that coreboot sets the SPI speed independently of having EFS set it, so read the values from EFS and re-program those. - Get rid of the current programming methods.
Tentative: - Additionally add a Kconfig to allow coreboot to ignore EFS (EFS is in the RO section, so this would allow us to change away from those speeds if needed.)