Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69212 )
Change subject: drivers/amd & soc/amd: Define bootblock postcodes ......................................................................
drivers/amd & soc/amd: Define bootblock postcodes
Postcodes 0x50 - 0x52 are used for bootblock functions. This change makes this standard across all AMD chips.
- bootblock_c_entry: 0x50 - bootblock_soc_early_init: 0x51 - bootblock_soc_init: 0x52
Stoney was previously using 0x90 for bootblock_soc_early_init.
Signed-off-by: Martin Roth gaumless@gmail.com Change-Id: I7b5de5887d36072b94e05602f787668818fd0d99 --- M src/drivers/amd/agesa/bootblock.c M src/soc/amd/common/block/cpu/noncar/bootblock.c A src/soc/amd/common/block/include/amdblocks/post_codes.h M src/soc/amd/stoneyridge/bootblock.c 4 files changed, 77 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/69212/1
diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index df9876a..5acddfd 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -4,6 +4,7 @@ #include <halt.h> #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> +#include <amdblocks/post_codes.h> #include <arch/bootblock.h> #include <cpu/amd/msr.h> #include <cpu/x86/mtrr.h> @@ -20,11 +21,15 @@
void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + bootblock_early_southbridge_init(); }
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); set_early_mtrrs();
@@ -36,6 +41,8 @@
asmlinkage void ap_bootblock_c_entry(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); set_early_mtrrs();
diff --git a/src/soc/amd/common/block/cpu/noncar/bootblock.c b/src/soc/amd/common/block/cpu/noncar/bootblock.c index 13bac18..c76ebb3 100644 --- a/src/soc/amd/common/block/cpu/noncar/bootblock.c +++ b/src/soc/amd/common/block/cpu/noncar/bootblock.c @@ -2,6 +2,7 @@
#include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/cpu.h> +#include <amdblocks/post_codes.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/cpu.h> @@ -12,6 +13,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + early_cache_setup(); write_resume_eip(); enable_pci_mmconf(); @@ -34,12 +37,17 @@
void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + fch_pre_init(); }
void bootblock_soc_init(void) { - u32 val = cpuid_eax(1); + u32 val; + post_code(POST_SOC_AMD_BOOTBLOCK_INIT); + + val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK)) { diff --git a/src/soc/amd/common/block/include/amdblocks/post_codes.h b/src/soc/amd/common/block/include/amdblocks/post_codes.h new file mode 100644 index 0000000..4537498 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/post_codes.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/** + * @file post_codes.h + */ + +/* + * The post codes 0x50-0x5f are reserved for use by SoCs. These values should + * not be used in other areas of coreboot, so should uniquely identify the SoC + * area. + * + * For AMD, we should unify the values between the various chips so that the + * same code means the same thing on each. + */ + +/** + * @brief Entering SoC bootblock + * + * coreboot entered the bootblock_c_entry function + */ + #define POST_SOC_AMD_BOOTBLOCK_ENTRY 0x50 + +/** + * @brief Entering SoC early init code + * + * coreboot entered the bootblock_soc_early_init function + */ + #define POST_SOC_AMD_BOOTBLOCK_INIT_EARLY 0x51 + + /** + * @brief Entered SoC bootblock init code + * + * coreboot entered the bootblock_soc_init function + */ + #define POST_SOC_AMD_BOOTBLOCK_INIT 0x52 diff --git a/src/soc/amd/stoneyridge/bootblock.c b/src/soc/amd/stoneyridge/bootblock.c index 0a67d9b..79b8945 100644 --- a/src/soc/amd/stoneyridge/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock.c @@ -13,6 +13,7 @@ #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <amdblocks/iomap.h> +#include <amdblocks/post_codes.h> #include <soc/pci_devs.h> #include <soc/cpu.h> #include <soc/southbridge.h> @@ -57,6 +58,8 @@
asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + post_code(POST_SOC_AMD_BOOTBLOCK_ENTRY); + enable_pci_mmconf(); amd_initmmio(); /* @@ -76,12 +79,15 @@
void bootblock_soc_early_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT_EARLY); + bootblock_fch_early_init(); - post_code(0x90); }
void bootblock_soc_init(void) { + post_code(POST_SOC_AMD_BOOTBLOCK_INIT); + if (CONFIG(AMD_SOC_CONSOLE_UART)) assert(CONFIG_UART_FOR_CONSOLE >= 0 && CONFIG_UART_FOR_CONSOLE <= 1);