[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Set UPDs for tuning eDP phy

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48733 )

Change subject: soc/amd/picasso: Set UPDs for tuning eDP phy
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soc/amd/picasso: Set UPDs for tuning eDP phy

Add UPDs for edp phy tuning adjust.

BUG=b:171269338
BRANCH=zork
TEST=Build, verify the parameter pass to picasso-fsp

Signed-off-by: Chris Wang 
Change-Id: I389bc4b5726f70bb1edfd858dba1c575cf68050b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48733
Tested-by: build bot (Jenkins) 
Reviewed-by: Nikolai Vyssotski 
Reviewed-by: EricR Lai 
---
M src/soc/amd/picasso/chip.h
M src/soc/amd/picasso/fsp_params.c
2 files changed, 35 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved
  Nikolai Vyssotski: Looks good to me, but someone else must approve

diff --git a/src/soc/amd/picasso/chip.h b/src/soc/amd/picasso/chip.h
index 66ac98d..9498303 100644
--- a/src/soc/amd/picasso/chip.h
+++ b/src/soc/amd/picasso/chip.h
@@ -57,6 +57,18 @@
    SD_EMMC_DRIVE_STRENGTH_D,
 };

+/* dpphy_override */
+enum sysinfo_dpphy_override {
+	ENABLE_DVI_TUNINGSET = 0x01,
+	ENABLE_HDMI_TUNINGSET = 0x02,
+	ENABLE_HDMI6G_TUNINGSET = 0x04,
+	ENABLE_DP_TUNINGSET = 0x08,
+	ENABLE_DP_HBR3_TUNINGSET = 0x10,
+	ENABLE_DP_HBR_TUNINGSET = 0x20,
+	ENABLE_DP_HBR2_TUNINGSET = 0x40,
+	ENABLE_EDP_TUNINGSET = 0x80,
+};
+
 struct soc_amd_picasso_config {
    struct soc_amd_common_config common_config;
    /*
@@ -221,6 +233,16 @@
    enum gpp_clk_req_setting gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
    /* If using an external 48MHz OSC for codec, will disable internal X48M_OSC */
    bool acp_i2s_use_external_48mhz_osc;
+
+	/* eDP phy tuning settings */
+	uint8_t dp_phy_override;
+
+	struct {
+		uint8_t dp_vs_pemph_level;
+		uint8_t deemph_6db4;
+		uint8_t boostadj;
+		uint16_t margin_deemph;
+	} edp_tuningset;
 };

#endif /* __PICASSO_CHIP_H__ */
diff --git a/src/soc/amd/picasso/fsp_params.c b/src/soc/amd/picasso/fsp_params.c
index c7befe4..3a27a16 100644
--- a/src/soc/amd/picasso/fsp_params.c
+++ b/src/soc/amd/picasso/fsp_params.c
@@ -142,6 +142,18 @@
    scfg->fch_ioapic_id = CONFIG_PICASSO_FCH_IOAPIC_ID;
 }

+static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
+			const struct soc_amd_picasso_config *cfg)
+{
+	if (cfg->dp_phy_override & ENABLE_EDP_TUNINGSET) {
+		scfg->DpPhyOverride = cfg->dp_phy_override;
+		scfg->DpVsPemphLevel = cfg->edp_tuningset.dp_vs_pemph_level;
+		scfg->MarginDeemPh = cfg->edp_tuningset.margin_deemph;
+		scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
+		scfg->BoostAdj = cfg->edp_tuningset.boostadj;
+	}
+}
+
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
    const struct soc_amd_picasso_config *cfg;
@@ -152,4 +164,5 @@
    fsp_fill_pcie_ddi_descriptors(scfg);
    fsp_assign_ioapic_upds(scfg);
    fsp_usb_oem_customization(scfg, cfg);
+	fsp_edp_tuning_upds(scfg, cfg);
 }