Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : } CB:44039 is now upstream and CB:45878 is close. This info can be obtained from the devicetree, with just a few small additions after rebasing on 45878 or later (my suggestions here): 1) I would add a `DEVTREE_CONST struct device *pd_muxes[4]" to `struct soc_intel_tigerlake_config`. 2) In volteer's mainboard devicetree, add the alias and the reference: ``` chip soc/intel/tigerlake use conn0 as pd_mux[0] use conn1 as pd_mux[1] ``` 3) Then get a ref to the SoC config here, and get the info from `pd_mux[i]->chip_info`