Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80467?usp=email )
Change subject: mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC ......................................................................
mb/google/brox: Set PCH_EC_PCH_INT_ODL pin as IOAPIC
Setting the EC interrupt GPIO as an APIC is able to solve many problems that we are currently seeing:
1. Routing through the APIC make the IRQ# associated with this pin unavailable to claim for other devices in the kernel. This is causing EC interrupts to not work. 2. Since EC interrupt are not working, we are not able to flash the EC from the DUT. 3. Also, the GPI_INT configuration does not allow us to set the polarity of the GPIO, which means that it is by default set as active high. As a result, we are seeing an excessive number of host command interrupts to the EC. This disappears when we change the configuration to APIC and set the polarity as INVERT.
BUG=b:319129926,b:324707182 BRANCH=None
TEST=1. After boot up, check if ec_cros_lpcs driver was successfully registered. Look for the following string: "cros_ec_lpcs GOOG0004:00: Chrome EC device registered" 2. Make sure can flash the EC image from the DUT 3. Make sure EC console is not getting continuous stream of host commands.
Change-Id: I74bff88d2ddbaf1f4b085c31d582bd66e18c438a Signed-off-by: Shelley Chen shchen@google.com --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/80467/1
diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 1464820..337fde1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -140,7 +140,7 @@ PAD_NC(GPP_C7, NONE),
/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ - PAD_CFG_GPI_INT_SWAPPED(GPP_D0, NONE, PLTRST, LEVEL), + PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST), /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */