[coreboot-gerrit] New patch to review for coreboot: soc/glk: select config CACHE_MRC_SETTINGS

[Hannah Williams]

Hannah Williams ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17821

-gerrit

commit ab8f1e07cdf27ec7582c9f260d471825fdff1459
Author: Hannah Williams 
Date:   Mon Oct 31 14:09:55 2016 -0700

soc/glk: select config CACHE_MRC_SETTINGS

Change-Id: Id214aadc3e508ecbfceda8ecc4c1e4ddd15d8895
    Signed-off-by: Hannah Williams 
---
 src/soc/intel/glk/Kconfig | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig
index 9d40e3b..f79d81f 100644
--- a/src/soc/intel/glk/Kconfig
+++ b/src/soc/intel/glk/Kconfig
@@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
    select SOC_INTEL_COMMON_GFX_OPREGION
    select ADD_VBT_DATA_FILE
    select SOC_INTEL_COMMON_RESET
+	select CACHE_MRC_SETTINGS

config CHROMEOS
    select CHROMEOS_RAMOOPS_DYNAMIC
@@ -125,6 +126,7 @@ config CONSOLE_UART_BASE_ADDRESS
    hex "MMIO base address for UART"
    default 0xde000000

+
 config SOC_UART_DEBUG
    bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE."
    default n
@@ -156,10 +158,6 @@ config VERSTAGE_ADDR
    help
      The base address (in CAR) where verstage should be linked

-config CACHE_MRC_SETTINGS
-	bool
-	default y
-
 config FSP_M_ADDR
    hex
    default 0xfef40000