Ravishankar Sarawadi (ravishankar.sarawadi@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16587
-gerrit
commit bd8e15c4e31f0174f3ae6a502e876e2c076d6d1e Author: Ravi Sarawadi ravishankar.sarawadi@intel.com Date: Mon Sep 26 14:48:18 2016 -0700
[WIP]soc/apollolake: Set package lelve MSR
Set package level MSRs after boot/suspend-cycle.
BUG=chrome-os-partner:56922 BRANCH=None
TEST=Use iotools rdmsr and 'powertop' to check MSRs Signed-off-by: Ravi Sarawadi ravishankar.sarawadi@intel.com
Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 --- src/soc/intel/apollolake/cpu.c | 11 +++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 1 + 2 files changed, 12 insertions(+)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 86fe3e1..8d02080 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -25,6 +25,7 @@ #include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> +#include <reg_script.h> #include <soc/cpu.h> #include <soc/smm.h>
@@ -62,6 +63,13 @@ static void read_cpu_topology(unsigned int *num_phys, unsigned int *num_virt) *num_phys = (msr.lo >> 16) & 0xffff; }
+/* Package level MSRs */ +static const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~12W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x8f0000dd8c00), + REG_SCRIPT_END +}; + /* * Do essential initialization tasks before APs can be fired up * @@ -73,6 +81,9 @@ static void pre_mp_init(void) { x86_setup_mtrrs_with_detect(); x86_mtrr_check(); + + /* Set package MSRs */ + reg_script_run(package_msr_script); }
/* Find CPU topology */ diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 22412af..78de6f8 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -39,6 +39,7 @@ void apollolake_init_cpus(struct device *dev); #define PREFETCH_L2_DISABLE (1 << 2)
#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610
#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) #define MSR_IA32_PQR_ASSOC 0xc8f