Hello Felix Singer, build bot (Jenkins), Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48412
to look at the new patch set (#3).
Change subject: nb/intel/sandybridge: Correct DMI PHY setup ......................................................................
nb/intel/sandybridge: Correct DMI PHY setup
The DMI PHY init sequence was written using trace dumps as a reference. While the code works, there's still room for improvement. For starters, it does not account for stepping-specific steps. It is unknown whether initializing DMI PHYs using a sequence for another stepping negatively affects system stability, but it likely does: should the DMI data link go down, the PCH disallows link retraining, which causes a system hang.
Moreover, most register writes are preceded by a dummy read, which is illogical: dummy reads to ensure a posted register write has completed need to be done after the register has been written to, and not before. What reference code is actually doing is a read-modify-write operation.
Following what reference code does, rewrite the DMI PHY setup sequence.
Tested on Asus P8Z77-V LX2, still boots with Ivy Bridge E1 CPU.
Change-Id: I2c2254a83e0ea8f8ec9d7290d88a6df1b7372d88 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/early_dmi.c 1 file changed, 181 insertions(+), 122 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/48412/3