[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/snowridge: add CPU and PCIe definitions for SNR

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Attention is currently required from: Jérémy Compostella, Shuo Liu.

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Change subject: soc/intel/snowridge: add CPU and PCIe definitions for SNR
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Patch Set 2:

(1 comment)

File src/include/cpu/intel/cpu_ids.h:

https://review.coreboot.org/c/coreboot/+/83314/comment/a1143fc3_e91f140b?usp... :
PS1, Line 86: #define CPUID_SNOWRIDGE_A0	0x80660
> Isn't it missing an extra tab for indentation ?

Yes, I've added it.