[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Enable LAN clock source usage

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30100

Change subject: mb/google/sarien: Enable LAN clock source usage
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mb/google/sarien: Enable LAN clock source usage

FSP defined a special clock source usage 0x70 for PCH LAN device, update
that to google sarien platform.

BUG=b:120003760
TEST=Boot up into OS, ethernet able to be listed in ifconfig.

Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8
Signed-off-by: Lijian Zhao 
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30100/1

diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index f487979..91bda9c 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -76,7 +76,7 @@

# PCIe port 9 for LAN
    register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[0]" = "8"
+	register "PcieClkSrcUsage[0]" = "PCIE_CLK_LAN"
    register "PcieClkSrcClkReq[0]" = "0"

# PCIe port 10 for M.2 2230 WLAN
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 5004abf..a960252 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -81,7 +81,7 @@

# PCIe port 9 for LAN
    register "PcieRpEnable[8]" = "1"
-	register "PcieClkSrcUsage[3]" = "8"
+	register "PcieClkSrcUsage[3]" = "PCIE_CLK_LAN"
    register "PcieClkSrcClkReq[3]" = "3"

# PCIe port 10 for M.2 2230 WLAN