Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/68486 )
(
4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8188: Rename SPM register ......................................................................
soc/mediatek/mt8188: Rename SPM register
The SPM register at offset 0x0 is often named as poweron_config_set in previous MediaTek SoCs. To use common driver, we rename it from poweron_config_en to poweron_config_set.
BUG=none TEST=emerge-geralt coreboot.
Signed-off-by: Bo-Chen Chen rex-bc.chen@mediatek.com Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486 Reviewed-by: Yidi Lin yidilin@google.com Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Yu-Ping Wu yupingso@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8188/pmif_clk.c M src/soc/mediatek/mt8188/spm.c 3 files changed, 26 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, but someone else must approve
diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 734a810..9c5a807 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -437,7 +437,7 @@ };
struct mtk_spm_regs { - u32 poweron_config_en; + u32 poweron_config_set; u32 spm_power_on_val0; u32 spm_power_on_val1; u32 spm_clk_con; diff --git a/src/soc/mediatek/mt8188/pmif_clk.c b/src/soc/mediatek/mt8188/pmif_clk.c index aac9b7b..0a94325 100644 --- a/src/soc/mediatek/mt8188/pmif_clk.c +++ b/src/soc/mediatek/mt8188/pmif_clk.c @@ -106,8 +106,8 @@ pmif_ulposc_config();
/* enable APB clock swinf */ - if (!READ32_BITFIELD(&mtk_spm->poweron_config_en, BCLK_CG_EN)) - SET32_BITFIELDS(&mtk_spm->poweron_config_en, BCLK_CG_EN, 1, + if (!READ32_BITFIELD(&mtk_spm->poweron_config_set, BCLK_CG_EN)) + SET32_BITFIELDS(&mtk_spm->poweron_config_set, BCLK_CG_EN, 1, PROJECT_CODE, 0xb16);
/* turn on ulposc */ diff --git a/src/soc/mediatek/mt8188/spm.c b/src/soc/mediatek/mt8188/spm.c index fd4648f..c87d1f0 100644 --- a/src/soc/mediatek/mt8188/spm.c +++ b/src/soc/mediatek/mt8188/spm.c @@ -440,7 +440,7 @@ /* set clock path for SPM */ setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x7ff); /* enable register control */ - write32(&mtk_spm->poweron_config_en, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); + write32(&mtk_spm->poweron_config_set, SPM_REGWR_CFG_KEY | BCLK_CG_EN_LSB); /* init power control register, dram will set this register */ write32(&mtk_spm->spm_power_on_val1, POWER_ON_VAL1_DEF); write32(&mtk_spm->pcm_pwr_io_en, 0);