Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75730?usp=email )
Change subject: mb/intel/mtlrvp: Add CPU power limit values ......................................................................
mb/intel/mtlrvp: Add CPU power limit values
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for mtlrvp baseboard.
BRANCH=None BUG=None TEST=Built the changes
Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757 Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai eric_lai@quanta.corp-partner.google.com Reviewed-by: Subrata Banik subratabanik@google.com --- M src/mainboard/intel/mtlrvp/Kconfig M src/mainboard/intel/mtlrvp/mainboard.c M src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc A src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c 5 files changed, 40 insertions(+), 0 deletions(-)
Approvals: Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index ea6c6cb..4f4526e 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -17,6 +17,7 @@ select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS + select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_METEORLAKE_U_P
diff --git a/src/mainboard/intel/mtlrvp/mainboard.c b/src/mainboard/intel/mtlrvp/mainboard.c index 9621294..2e515f7 100644 --- a/src/mainboard/intel/mtlrvp/mainboard.c +++ b/src/mainboard/intel/mtlrvp/mainboard.c @@ -35,6 +35,13 @@
if (CONFIG(EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); + + variant_devtree_update(); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ }
static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h index f755ff0..726a617 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/include/baseboard/variants.h @@ -20,4 +20,7 @@ /* Function to initialize memory params based on variant */ const struct mb_cfg *variant_memory_params(void);
+/* Modify devictree settings during ramstage */ +void variant_devtree_update(void); + #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc index cc5cdc1..dafb64b 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/Makefile.inc @@ -2,3 +2,4 @@
bootblock-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c new file mode 100644 index 0000000..aee3d88 --- /dev/null +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/ramstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_2, + .cpu_tdp = 15, + .pl1_min_power = 10000, + .pl1_max_power = 15000, + .pl2_min_power = 57000, + .pl2_max_power = 57000, + .pl4_power = 114000 + }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_cpu_power_limits(limits, total_entries); +}