20 Aug
2020
20 Aug
'20
9:27 a.m.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44626 )
Change subject: soc/intel/tigerlake: Enable long cr50 ready pulses ......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11
Gerrit-Change-Number: 44626
Gerrit-PatchSet: 1
Gerrit-Owner: Jes Klinke jbk@chromium.org
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Jes Klinke jbk@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 20 Aug 2020 07:27:50 +0000
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