Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62744 )
Change subject: mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants ......................................................................
mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants
This sets EPP value to be 45% for all Adl RVP variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms. But on Intel Alderlake EPP ratio of 45% is recommended for optimal power and performance on Chrome platforms.
TEST= Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang cliff.huang@intel.corp-partner.google.com Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Bora Guvendik bora.guvendik@intel.com --- M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/adlrvp/devicetree_n.cb 3 files changed, 12 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Bora Guvendik: Looks good to me, approved
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index a4f8594..8847d88 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -168,6 +168,10 @@
register "cnvi_bt_audio_offload" = "true"
+ # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index 4a41df6..deff4dc 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -143,6 +143,10 @@ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "1"
+ # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .gspi[1] = { diff --git a/src/mainboard/intel/adlrvp/devicetree_n.cb b/src/mainboard/intel/adlrvp/devicetree_n.cb index d38c010..2b7eca6 100644 --- a/src/mainboard/intel/adlrvp/devicetree_n.cb +++ b/src/mainboard/intel/adlrvp/devicetree_n.cb @@ -127,6 +127,10 @@
register "cnvi_bt_audio_offload" = "true"
+ # set EPP to 45%: 45 * 256/100 = 115 = 0x73 + register "enable_energy_perf_pref" = "true" + register "energy_perf_pref_value" = "0x73" + # Intel Common SoC Config register "common_soc_config" = "{ .i2c[0] = {