[coreboot-gerrit] Change in coreboot[master]: lippert/frontrunner-af: Use common cimx/sb800 ASL

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50657 )

Change subject: lippert/frontrunner-af: Use common cimx/sb800 ASL
......................................................................

lippert/frontrunner-af: Use common cimx/sb800 ASL

Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50657
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/mainboard/lippert/frontrunner-af/dsdt.asl
M src/southbridge/amd/cimx/sb800/acpi/lpc.asl
2 files changed, 3 insertions(+), 125 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl
index 48d8375..1839b64 100644
--- a/src/mainboard/lippert/frontrunner-af/dsdt.asl
+++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl
@@ -189,130 +189,15 @@
    			#include "acpi/sata.asl"
    		} /* end STCR */

-			Device(UOH1) {
-				Name(_ADR, 0x00120000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH1 */
-
-			Device(UOH2) {
-				Name(_ADR, 0x00120002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH2 */
-
-			Device(UOH3) {
-				Name(_ADR, 0x00130000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH3 */
-
-			Device(UOH4) {
-				Name(_ADR, 0x00130002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH4 */
-
-			Device(UOH5) {
-				Name(_ADR, 0x00160000)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UOH6) {
-				Name(_ADR, 0x00160002)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UOH5 */
-
-			Device(UEH1) {
-				Name(_ADR, 0x00140005)
-				Name(_PRW, Package() {0x0B, 3})
-			} /* end UEH1 */
+			#include <southbridge/amd/cimx/sb800/acpi/usb.asl>

Device(SBUS) {
    			Name(_ADR, 0x00140000)
    		} /* end SBUS */

-			Device(AZHD) {
-				Name(_ADR, 0x00140002)
-				OperationRegion(AZPD, PCI_Config, 0x00, 0x100)
-					Field(AZPD, AnyAcc, NoLock, Preserve) {
-					offset (0x42),
-					NSDI, 1,
-					NSDO, 1,
-					NSEN, 1,
-					offset (0x44),
-					IPCR, 4,
-					offset (0x54),
-					PWST, 2,
-					, 6,
-					PMEB, 1,
-					, 6,
-					PMST, 1,
-					offset (0x62),
-					MMCR, 1,
-					offset (0x64),
-					MMLA, 32,
-					offset (0x68),
-					MMHA, 32,
-					offset (0x6C),
-					MMDT, 16,
-				}
-			} /* end AZHD */
+			#include <southbridge/amd/cimx/sb800/acpi/audio.asl>

-			Device(LIBR) {
-				Name(_ADR, 0x00140003)
-
-				/* Real Time Clock Device */
-				Device(RTC0) {
-					Name(_HID, EISAID("PNP0B00"))   /* AT Real Time Clock (not PIIX4 compatible) */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){8}
-						IO(Decode16,0x0070, 0x0070, 0, 2)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */
-
-				Device(TMR) {	/* Timer */
-					Name(_HID,EISAID("PNP0100"))	/* System Timer */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){0}
-						IO(Decode16, 0x0040, 0x0040, 0, 4)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.TMR) */
-
-				Device(SPKR) {	/* Speaker */
-					Name(_HID,EISAID("PNP0800"))	/* AT style speaker */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x0061, 0x0061, 0, 1)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */
-
-				Device(PIC) {
-					Name(_HID,EISAID("PNP0000"))	/* AT Interrupt Controller */
-					Name(_CRS, ResourceTemplate() {
-						IRQNoFlags(){2}
-						IO(Decode16,0x0020, 0x0020, 0, 2)
-						IO(Decode16,0x00A0, 0x00A0, 0, 2)
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.PIC) */
-
-				Device(MAD) { /* 8257 DMA */
-					Name(_HID,EISAID("PNP0200"))	/* Hardware Device ID */
-					Name(_CRS, ResourceTemplate() {
-						DMA(Compatibility,BusMaster,Transfer8){4}
-						IO(Decode16, 0x0000, 0x0000, 0x10, 0x10)
-						IO(Decode16, 0x0081, 0x0081, 0x01, 0x03)
-						IO(Decode16, 0x0087, 0x0087, 0x01, 0x01)
-						IO(Decode16, 0x0089, 0x0089, 0x01, 0x03)
-						IO(Decode16, 0x008F, 0x008F, 0x01, 0x01)
-						IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20)
-					}) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */
-				} /* End Device(_SB.PCI0.LpcIsaBr.MAD) */
-
-				Device(COPR) {
-					Name(_HID,EISAID("PNP0C04"))	/* Math Coprocessor */
-					Name(_CRS, ResourceTemplate() {
-						IO(Decode16, 0x00F0, 0x00F0, 0, 0x10)
-						IRQNoFlags(){13}
-					})
-				} /* End Device(_SB.PCI0.LpcIsaBr.COPR) */
-				#include "acpi/superio.asl"
-			} /* end LIBR */
+			#include <southbridge/amd/cimx/sb800/acpi/lpc.asl>

/* PCI bridge */
    		Device(PIBR) {
diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
index 507a8b8..dc72061 100644
--- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
+++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl
@@ -2,9 +2,6 @@

Device(LIBR) {
    Name(_ADR, 0x00140003)
-	/* Method(_INI) {
-	*	DBGO("\_SB\PCI0\LpcIsaBr\_INI\n")
-	} */ /* End Method(_SB.SBRDG._INI) */

/* Real Time Clock Device */
    Device(RTC0) {
@@ -12,7 +9,6 @@
    	Name(_CRS, ResourceTemplate() {
    		IRQNoFlags(){8}
    		IO(Decode16,0x0070, 0x0070, 0, 2)
-			/* IO(Decode16,0x0070, 0x0070, 0, 4) */
    	})
    } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */

@@ -21,7 +17,6 @@
    	Name(_CRS, ResourceTemplate() {
    		IRQNoFlags(){0}
    		IO(Decode16, 0x0040, 0x0040, 0, 4)
-			/* IO(Decode16, 0x0048, 0x0048, 0, 4) */
    	})
    } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */

@@ -38,8 +33,6 @@
    		IRQNoFlags(){2}
    		IO(Decode16,0x0020, 0x0020, 0, 2)
    		IO(Decode16,0x00A0, 0x00A0, 0, 2)
-			/* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */
-			/* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */
    	})
    } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */