[coreboot-gerrit] Change in coreboot[master]: mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s

[Matt DeVillier (Code Review)]

Matt DeVillier has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48978 )

Change subject: mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s
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mb/google/{beltino,fizz,jecht}: Set Tianocore boot timeout to 5s

These Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.

Test: build/boot one of each variant, ensure boot splash/menu
prompt visible regardless of display init type used.

Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Michael Niewöhner 
---
M src/mainboard/google/beltino/Kconfig
M src/mainboard/google/fizz/Kconfig
M src/mainboard/google/jecht/Kconfig
3 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig
index cbf9dc4..9cd71a8 100644
--- a/src/mainboard/google/beltino/Kconfig
+++ b/src/mainboard/google/beltino/Kconfig
@@ -62,4 +62,8 @@
 config PCIEXP_AER
    def_bool n

+config TIANOCORE_BOOT_TIMEOUT
+	int
+	default 5
+
 endif # BOARD_GOOGLE_BASEBOARD_BELTINO
diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig
index e09f853..548f2eb 100644
--- a/src/mainboard/google/fizz/Kconfig
+++ b/src/mainboard/google/fizz/Kconfig
@@ -99,4 +99,8 @@
 config USE_PM_ACPI_TIMER
    default n

+config TIANOCORE_BOOT_TIMEOUT
+	int
+	default 5
+
 endif # BOARD_GOOGLE_BASEBOARD_FIZZ
diff --git a/src/mainboard/google/jecht/Kconfig b/src/mainboard/google/jecht/Kconfig
index 4851bd7..5955565 100644
--- a/src/mainboard/google/jecht/Kconfig
+++ b/src/mainboard/google/jecht/Kconfig
@@ -59,4 +59,8 @@
 config PCIEXP_AER
    def_bool n

+config TIANOCORE_BOOT_TIMEOUT
+	int
+	default 5
+
 endif