[coreboot-gerrit] New patch to review for coreboot: northbridge/amd/lx: Remove commented code

[HAOUAS Elyes]

HAOUAS Elyes ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16891

-gerrit

commit ba7fc2b8ec8dd7d7467a1f1c1fbd98d9183315bb
Author: Elyes HAOUAS 
Date:   Wed Oct 5 18:40:51 2016 +0200

northbridge/amd/lx: Remove commented code

Change-Id: I37c1674ee380936aba797e24897593fcca3b0269
    Signed-off-by: Elyes HAOUAS 
---
 src/northbridge/amd/lx/northbridge.c | 24 ------------------------
 src/northbridge/amd/lx/pll_reset.c   | 29 -----------------------------
 2 files changed, 53 deletions(-)

diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c
index 4b6090f..f0304be 100644
--- a/src/northbridge/amd/lx/northbridge.c
+++ b/src/northbridge/amd/lx/northbridge.c
@@ -293,37 +293,17 @@ static void enable_shadow(device_t dev)

static void northbridge_init(device_t dev)
 {
-	//msr_t msr;

printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);

enable_shadow(dev);
-	/*
-	 * Swiss cheese
-	 */
-	//msr = rdmsr(MSR_GLIU0_SHADOW);

-	//msr.hi |= 0x3;
-	//msr.lo |= 0x30000;
-
-	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU0_SHADOW, msr.hi, msr.lo);
-	//printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MSR_GLIU1_SHADOW, msr.hi, msr.lo);
 }

static void northbridge_set_resources(struct device *dev)
 {
    uint8_t line;

-#if 0
-	struct resource *res;
-	for (res = dev->resource_list; res; res = res->next) {
-
-		// andrei: do not change the base address, it will make the VSA virtual registers unusable
-		//pci_set_resource(dev, res);
-		// FIXME: static allocation may conflict with dynamic mappings!
-	}
-#endif
-
    struct bus *bus;
    for (bus = dev->link_list; bus; bus = bus->next) {
    	if (bus->children) {
@@ -400,12 +380,8 @@ static void pci_domain_enable(device_t dev)
    cpubug();
    chipsetinit();

-	// print_conf();
-
    do_vsmbios();		// do the magic stuff here, so prepare your tambourine;)

-	// print_conf();
-
    graphics_init();
 }

diff --git a/src/northbridge/amd/lx/pll_reset.c b/src/northbridge/amd/lx/pll_reset.c
index 318c7a1..d98a8ea 100644
--- a/src/northbridge/amd/lx/pll_reset.c
+++ b/src/northbridge/amd/lx/pll_reset.c
@@ -65,21 +65,6 @@ static void pll_reset(void)
    return;
 }

-#if 0 // Unused
-static unsigned int CPUSpeed(void)
-{
-	unsigned int speed;
-	msr_t msr;
-
-	msr = rdmsr(GLCP_SYS_RSTPLL);
-	speed = ((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) / 10;
-	if ((((((msr.hi >> RSTPLL_UPPER_CPUMULT_SHIFT) & 0x1F) + 1) * 333) % 10) > 5) {
-		++speed;
-	}
-	return (speed);
-}
-#endif
-
 unsigned int GeodeLinkSpeed(void)
 {
    unsigned int speed;
@@ -92,17 +77,3 @@ unsigned int GeodeLinkSpeed(void)
    }
    return (speed);
 }
-
-#if 0 // Unused
-static unsigned int PCISpeed(void)
-{
-	msr_t msr;
-
-	msr = rdmsr(GLCP_SYS_RSTPLL);
-	if (msr.hi & (1 << RSTPPL_LOWER_PCISPEED_SHIFT)) {
-		return (66);
-	} else {
-		return (33);
-	}
-}
-#endif