[coreboot-gerrit] Change in coreboot[master]: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61722 )

Change subject: mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version
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mb/google/brya: Enable GPIO PM dynamically based on cr50 FW version

cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.

BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/mainboard.c
2 files changed, 28 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/61722/1

diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index 386aa11..04c8f6a 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -44,6 +44,7 @@
    select MEMORY_SOLDERDOWN if !BOARD_GOOGLE_BANSHEE
    select SOC_INTEL_ALDERLAKE_PCH_P
    select SYSTEM_TYPE_LAPTOP
+	select CR50_USE_LONG_INTERRUPT_PULSES

config BOARD_GOOGLE_BASEBOARD_BRASK
    def_bool n
diff --git a/src/mainboard/google/brya/mainboard.c b/src/mainboard/google/brya/mainboard.c
index 536eabc..3496cf6 100644
--- a/src/mainboard/google/brya/mainboard.c
+++ b/src/mainboard/google/brya/mainboard.c
@@ -2,9 +2,13 @@

#include <baseboard/variants.h>
 #include <device/device.h>
+#include <drivers/i2c/tpm/tpm.h>
 #include <ec/ec.h>
 #include <soc/ramstage.h>
 #include <fw_config.h>
+#include <security/tpm/tss.h>
+#include <soc/gpio.h>
+#include <soc/ramstage.h>

static void add_fw_config_oem_string(const struct fw_config *config, void *arg)
 {
@@ -24,6 +28,29 @@

void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
 {
+	int ret;
+
+	ret = tlcl_lib_init();
+	if (ret != VB2_SUCCESS) {
+		printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
+		return;
+	}
+
+	if (cr50_is_long_interrupt_pulse_enabled()) {
+		printk(BIOS_INFO, "Enabling GPIO PM b/c CR50 has long IRQ pulse support\n");
+		config->gpio_override_pm = 0;
+	} else {
+		printk(BIOS_INFO, "Disabling GPIO PM b/c CR50 does not have long IRQ pulse "
+		       "support\n");
+		config->gpio_override_pm = 1;
+		config->gpio_pm[COMM_0] = 0;
+		config->gpio_pm[COMM_1] = 0;
+		config->gpio_pm[COMM_2] = 0;
+		config->gpio_pm[COMM_3] = 0;
+		config->gpio_pm[COMM_4] = 0;
+		config->gpio_pm[COMM_5] = 0;
+	}
+
    variant_update_soc_chip_config(config);
 }