Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34157 )
Change subject: soc/intel/cannonlake: Add CFL S62 and H82 device Ids ......................................................................
soc/intel/cannonlake: Add CFL S62 and H82 device Ids
- CFL S62 and H82 a.k.a CFL refresh S & H platforms.
- Add CFL S62 and H82 specific CPU, SA, IGD, PCH PCI device Id's in report_platform.c and respective common block driver.
- Add cannonlake PCH-H SPI1, SPI2, SPI3, and SPI flash controller PCI id's in common block spi driver.
TEST= build, boot to both Linux & windows OS on CFL refresh platforms and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan lean.sheng.tan@intel.com Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4 --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/systemagent/systemagent.c 8 files changed, 49 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34157/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 35c457a..071eb51 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2730,6 +2730,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246 0xa309 +#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246 0xa30e #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480 #define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481 #define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482 @@ -3001,6 +3003,10 @@ #define PCI_DEVICE_ID_INTEL_CNL_SPI1 0x9dab #define PCI_DEVICE_ID_INTEL_CNL_SPI2 0x9dfb #define PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI 0x9da4 +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI0 0xA32A +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI1 0xA32B +#define PCI_DEVICE_ID_INTEL_CNP_H_SPI2 0xA37B +#define PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI 0xA324 #define PCI_DEVICE_ID_INTEL_ICP_SPI0 0x34aa #define PCI_DEVICE_ID_INTEL_ICP_SPI1 0x34ab #define PCI_DEVICE_ID_INTEL_ICP_SPI2 0x34fb @@ -3040,8 +3046,11 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A #define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 -#define PCI_DEVICE_ID_INTEL_CFL_H_GT2 0x3e9b +#define PCI_DEVICE_ID_INTEL_CFL_H_GT2_0 0x3e9b +#define PCI_DEVICE_ID_INTEL_CFL_H_GT2_1 0x3e94 #define PCI_DEVICE_ID_INTEL_CFL_S_GT2 0x3e92 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT 0x3e98 +#define PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS 0x3e9a #define PCI_DEVICE_ID_INTEL_ICL_GT0_ULT 0x8A70 #define PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT 0x8A71 #define PCI_DEVICE_ID_INTEL_ICL_GT1_ULT 0x8A40 @@ -3102,7 +3111,10 @@ #define PCI_DEVICE_ID_INTEL_WHL_ID_Wx2 0x3E35 #define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 #define PCI_DEVICE_ID_INTEL_CFL_ID_H 0x3ec4 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Hx8 0x3e20 #define PCI_DEVICE_ID_INTEL_CFL_ID_S 0x3ec2 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT 0x3e30 +#define PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS 0x3e31 #define PCI_DEVICE_ID_INTEL_ICL_ID_U 0x8A12 #define PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2 0x8A02 #define PCI_DEVICE_ID_INTEL_ICL_ID_Y 0x8A10 @@ -3204,6 +3216,8 @@ #define PCH_CNL_H_DT_SUPER 0xa280 #define PCH_CNP_H_MOBILE_Q370 0xa306 #define PCH_CNP_H_MOBILE_QM370 0xa30c +#define PCH_CNP_H_MOBILE_C246 0xa309 +#define PCH_CNP_H_MOBILE_CM246 0xa30e
/* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index e0c9194..e9b5e09 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015-2018 Intel Corporation. + * Copyright (C) 2015-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -40,6 +40,8 @@ { CPUID_WHISKEYLAKE_V0, "Whiskeylake V0" }, { CPUID_WHISKEYLAKE_W0, "Whiskeylake W0" }, { CPUID_COFFEELAKE_U0, "Coffeelake U0 (6+2)" }, + { CPUID_COFFEELAKE_P0, "Coffeelake P0" }, + { CPUID_COFFEELAKE_R0, "Coffeelake R0" }, { CPUID_COMETLAKE_U_A0, "Cometlake-U A0 (6+2)" }, { CPUID_COMETLAKE_U_K0_S0, "Cometlake-U K0/S0 (6+2)/(4+2)" }, { CPUID_COMETLAKE_H_S_6_2_P0, "Cometlake-H/S P0 (6+2)" }, @@ -56,7 +58,10 @@ { PCI_DEVICE_ID_INTEL_WHL_ID_Wx4, "Whiskeylake W (4+2)" }, { PCI_DEVICE_ID_INTEL_WHL_ID_Wx2, "Whiskeylake W (2+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_H, "Coffeelake-H" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Hx8, "Coffeelake-H (8+2)" }, { PCI_DEVICE_ID_INTEL_CFL_ID_S, "Coffeelake-S" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT, "Coffeelake-S DT(8+2)" }, + { PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS, "Coffeelake-S WS(8+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT, "CometLake-U (4+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_2_2, "CometLake-U (2+2)" }, { PCI_DEVICE_ID_INTEL_CML_ULT_6_2, "CometLake-U (6+2)" }, @@ -76,6 +81,8 @@ { PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, "Cannonlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, "Cannonlake-H Q370" }, { PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, "Cannonlake-H QM370" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, "Cannonlake-H C246" }, + { PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, "Cannonlake-H CM246" }, { PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC, "Cometlake-U Super" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC, "Cometlake-Y Premium" }, { PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC, "Cometlake-U Premium" }, @@ -98,8 +105,11 @@ { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2" }, { PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" }, { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, - { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_H_GT2_0, "Coffeelake-H GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_H_GT2_1, "Coffeelake-H Xeon (6+2) GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT, "Coffeelake-S (8+2) GT2" }, + { PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS, "Coffeelake-S Xeon(8+2) GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_2, "CometLake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CML_GT2_ULT_1, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index e98b5dd..4850462 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -75,6 +75,8 @@ { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0 }, { X86_VENDOR_INTEL, CPUID_COFFEELAKE_D0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0 }, + { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_A0 }, { X86_VENDOR_INTEL, CPUID_ICELAKE_B0 }, { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0 }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ed9ae00..7a7e14d 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2017-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -149,8 +149,11 @@ PCI_DEVICE_ID_INTEL_SKL_GT2_SHALM, PCI_DEVICE_ID_INTEL_SKL_GT2_SWKSM, PCI_DEVICE_ID_INTEL_SKL_GT4_SHALM, - PCI_DEVICE_ID_INTEL_CFL_H_GT2, + PCI_DEVICE_ID_INTEL_CFL_H_GT2_0, + PCI_DEVICE_ID_INTEL_CFL_H_GT2_1, PCI_DEVICE_ID_INTEL_CFL_S_GT2, + PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_DT, + PCI_DEVICE_ID_INTEL_CFL_S_GT2x8_WS, PCI_DEVICE_ID_INTEL_ICL_GT0_ULT, PCI_DEVICE_ID_INTEL_ICL_GT0_5_ULT, PCI_DEVICE_ID_INTEL_ICL_GT1_ULT, diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 0f37a643..9605235 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -42,7 +42,8 @@ #define CPUID_WHISKEYLAKE_W0 0x806eb #define CPUID_COFFEELAKE_D0 0x806ea #define CPUID_COFFEELAKE_U0 0x906ea - +#define CPUID_COFFEELAKE_P0 0x906ec +#define CPUID_COFFEELAKE_R0 0x906ed #define CPUID_ICELAKE_A0 0x706e0 #define CPUID_ICELAKE_B0 0x706e1 #define CPUID_COMETLAKE_U_A0 0xa0660 diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 54c7706..20a459c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corp. + * Copyright (C) 2017-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -156,6 +156,8 @@ PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC, PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370, PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_C246, + PCI_DEVICE_ID_INTEL_CNP_H_LPC_CM246, PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 85db5cf..af5087f 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -67,6 +67,10 @@ PCI_DEVICE_ID_INTEL_CNL_SPI1, PCI_DEVICE_ID_INTEL_CNL_SPI2, PCI_DEVICE_ID_INTEL_CNL_HWSEQ_SPI, + PCI_DEVICE_ID_INTEL_CNP_H_SPI0, + PCI_DEVICE_ID_INTEL_CNP_H_SPI1, + PCI_DEVICE_ID_INTEL_CNP_H_SPI2, + PCI_DEVICE_ID_INTEL_CNP_H_HWSEQ_SPI, PCI_DEVICE_ID_INTEL_ICP_SPI0, PCI_DEVICE_ID_INTEL_ICP_SPI1, PCI_DEVICE_ID_INTEL_ICP_SPI2, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index a93db65..92bd732 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017-2018 Intel Corporation. + * Copyright (C) 2017-2019 Intel Corporation. * Copyright (C) 2019 Siemens AG * * This program is free software; you can redistribute it and/or modify @@ -357,7 +357,10 @@ PCI_DEVICE_ID_INTEL_KBL_ID_DT_2, PCI_DEVICE_ID_INTEL_CFL_ID_U, PCI_DEVICE_ID_INTEL_CFL_ID_H, + PCI_DEVICE_ID_INTEL_CFL_ID_Hx8, PCI_DEVICE_ID_INTEL_CFL_ID_S, + PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_DT, + PCI_DEVICE_ID_INTEL_CFL_ID_Sx8_WS, PCI_DEVICE_ID_INTEL_ICL_ID_U, PCI_DEVICE_ID_INTEL_ICL_ID_U_2_2, PCI_DEVICE_ID_INTEL_ICL_ID_Y,