Stefan Reinauer (stefan.reinauer@coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9262
-gerrit
commit bc33b499114dd33da87384fa47303cb74abe0cd6 Author: Duncan Laurie dlaurie@chromium.org Date: Fri Oct 3 15:34:09 2014 -0700
broadwell: Fix building with USE=quiet-cb
This function needs to be available in different LOGLEVELs.
BUG=chrome-os-partner:28234 BRANCH=samus TEST=USE=quiet-cb emerge-samus coreboot
Change-Id: Ib56995db64a7417a637eb8a93350fc40e6f83340 Signed-off-by: Stefan Reinauer reinauer@chromium.org Original-Commit-Id: 716d26c82a7df1dccf8956f301ab0e103fcedcff Original-Change-Id: Ia8f0d05af24c9070c8c9241a3a7e137f845d1cab Original-Signed-off-by: Duncan Laurie dlaurie@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/221540 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org --- src/soc/intel/broadwell/me_status.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 31eff3c..033e4e2 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -27,6 +27,12 @@ #include <broadwell/me.h> #include <delay.h>
+static inline void me_read_dword_ptr(void *ptr, int offset) +{ + u32 dword = pci_read_config32(PCH_DEV_ME, offset); + memcpy(ptr, &dword, sizeof(dword)); +} + #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
/* HFS1[3:0] Current Working State Values */ @@ -201,12 +207,6 @@ static const char *me_progress_policy_values[] = { "Required VSCC values for flash parts do not match", };
-static inline void me_read_dword_ptr(void *ptr, int offset) -{ - u32 dword = pci_read_config32(PCH_DEV_ME, offset); - memcpy(ptr, &dword, sizeof(dword)); -} - void intel_me_status(void) { struct me_hfs _hfs, *hfs = &_hfs;