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Hello Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84349?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins)
Change subject: soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI ......................................................................
soc/intel/common/block/acpi: exclude DMI fixed memory range if no DMI
In newer SOC, such as PTL, there is no DMI. Exclude DMI memory range in northbridge.asl if DMI_BASE_SIZE is '0'
BUG=b:348678529 TEST=Build CB with DMI_BASE_SIZE set to '0' in the SOC directory. Boot to OS and check ACPI PDRC device from the ACPI DSDT table. There should not have an entry for DMI in its _CRS method.
Verified on Intel® Simics® Pre Silicon Simulation platform for PTL using google/fatcat mainboard.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: I971af2eb214b5940fa09d9dc0f9717bb5f0dfb4d --- M src/soc/intel/common/block/acpi/acpi/northbridge.asl 1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/84349/6