[coreboot-gerrit] New patch to review for coreboot: 078d9e5 libpayload dwc2: sent address of buffer should be bus address

[Patrick Georgi]

Patrick Georgi ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9455

-gerrit

commit 078d9e5aa35200b262fcded2fe87d2b9c7bbaed0
Author: Ionela Voinescu 
Date:   Mon Feb 2 15:35:44 2015 +0000

libpayload dwc2: sent address of buffer should be bus address

The address of the output buffer sent to the device should be
    the bus address and not the virtual address.

BUG=chrome-os-partner:31438
    TEST=tested on Pistachio FPGA and bring up board;
         USB works properly after this change
    BRANCH=none

Change-Id: I5c9d199e17c3f4303095ad73f4980d32d04c6118
    Signed-off-by: Patrick Georgi 
    Original-Commit-Id: 942c385c112c2a4e409da806548081d3e2f8f438
    Original-Change-Id: I0c06196501a968a72cb3f2c7dd1027bb22cdaada
    Original-Signed-off-by: Ionela Voinescu 
    Original-Reviewed-on: https://chromium-review.googlesource.com/245387
    Original-Reviewed-by: David Hendricks 
    Original-Reviewed-by: Julius Werner 
---
 payloads/libpayload/drivers/usb/dwc2.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c
index 0830c9e..1102711 100644
--- a/payloads/libpayload/drivers/usb/dwc2.c
+++ b/payloads/libpayload/drivers/usb/dwc2.c
@@ -253,7 +253,8 @@ dwc2_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir,
    	memcpy(aligned_buf, data_buf, size);

writel(hctsiz.d32, &reg->host.hchn[ch_num].hctsizn);
-	writel((uint32_t)aligned_buf, &reg->host.hchn[ch_num].hcdman);
+	writel((uint32_t)virt_to_bus(aligned_buf),
+		&reg->host.hchn[ch_num].hcdman);
    writel(hcchar.d32, &reg->host.hchn[ch_num].hccharn);

ret = wait_for_complete(ep, ch_num);