Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro, Paul Menzel, Ravishankar Sarawadi.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81954?usp=email )
Change subject: cpu/intel/microcode: Defer microcode patching until after DRAM init
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81954/comment/1c59126f_fda7ac8e :
PS1, Line 9: Follows Intel SoC recommendation to avoid potential cache contention
: issues during early (pre-DRAM) microcode loading.
Please document the source, maybe even section in the datasheet.
https://review.coreboot.org/c/coreboot/+/81954/comment/9962ac25_37ca2b23 :
PS1, Line 17: [DEBUG] microcode: sig=0xa06a4 pf=0x80 revision=0x19
: [INFO ] CBFS: Found 'cpu_microcode_a06a4.bin' @0x1d9c0 size 0x21400
: in mcache @0xfef89680
: [INFO ] VB2:vb2_digest_init() 136192 bytes, hash algo 2, HW
: acceleration enabled
: [INFO ] microcode: load microcode patch
: [ERROR] microcode: Update failed
Indent by four spaces and do not wrap the lines. […]
Acknowledged
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