Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42441 )
Change subject: mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms ......................................................................
mb/google/hatch: Set Reset Power Cycle Duration for hatch platforms
Currently, coreboot doesn't set UPD FSPS PchPmPwrCycDur (Reset Power Cycle Duration). So, FSP set default value(4sec) to PchPmPwrCycDur. This adds around ~5 seconds of delay during power cycle or global reset. So, this patch set PchPmPwrCycDur to 1 second to minimize the delay.
System behaviour for Power Cylce or Global Reset: With default value: S0->S3->S5 -> [~5 seconds delay]-> S5->S3->S0
With the change: S0->S3->S5 -> [~2 seconds delay]-> S5->S3->S0
Signed-off-by: Sridhar Siricilla sridhar.siricilla@intel.com Change-Id: I368c6716a92e06903a872f9e87ae0698eab95bdd --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/42441/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2d3156a..04221af 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -143,6 +143,7 @@ register "PchPmSlpS4MinAssert" = "1" # 1s register "PchPmSlpSusMinAssert" = "1" # 500ms register "PchPmSlpAMinAssert" = "3" # 2s + register "PchPmPwrCycDur" = "1" # 1s
# Enable Audio DSP oscillator qualification for S0ix register "cppmvric2_adsposcdis" = "1"