[coreboot-gerrit] [L] Change in coreboot[master]: mb/intel: Add 2 SPR sockets CRB Archer City

[Johnny Lin (Code Review)]

Attention is currently required from: Patrick Rudolph, Simon Chou, Paul Menzel, Shuming Chu (Shuming), Arthur Heymans, Lean Sheng Tan, Juan Sanchez, Shelly Chang.

Johnny Lin has uploaded a new patch set (#32) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 )

Change subject: mb/intel: Add 2 SPR sockets CRB Archer City
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mb/intel: Add 2 SPR sockets CRB Archer City

Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids
Scalable Processor chipset. The chipset also includes Emmitsburg PCH.
It was tested with LinuxBoot payload on both dual and single socket
configurations.
The multisocket support depends on Change-Id:
I4a593252bb7f68494f4ccce215ac9cf1eb19b190

Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17
Signed-off-by: Jonathan Zhang 
Signed-off-by: Johnny Lin 
---
A src/mainboard/intel/archercity_crb/Kconfig
A src/mainboard/intel/archercity_crb/Kconfig.name
A src/mainboard/intel/archercity_crb/Makefile.inc
A src/mainboard/intel/archercity_crb/acpi/platform.asl
A src/mainboard/intel/archercity_crb/board.fmd
A src/mainboard/intel/archercity_crb/board_info.txt
A src/mainboard/intel/archercity_crb/bootblock.c
A src/mainboard/intel/archercity_crb/devicetree.cb
A src/mainboard/intel/archercity_crb/dsdt.asl
A src/mainboard/intel/archercity_crb/include/mainboard_ras.h
A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h
A src/mainboard/intel/archercity_crb/ramstage.c
A src/mainboard/intel/archercity_crb/romstage.c
13 files changed, 483 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/32