Hello Patrick Rudolph, Subrata Banik, Duncan Laurie, build bot (Jenkins), Nico Huber, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31445
to look at the new patch set (#7).
Change subject: soc/intel/cannonlake: Add a power control workaround for SD controller ......................................................................
soc/intel/cannonlake: Add a power control workaround for SD controller
SD_VDD1_PWR_EN# does not de-assert during SDXC D3 or when SD card is not inserted. For platforms using SD_VDD1_PWR_EN# as active high, the SDXC card connector is always powered and may impact system power.
Workaround is to change the pad ownership of SD_VDD1_PWR_EN to GPIO and force the TX buffer to low in _PS3. And restore the pad mode to native funtion in _PS0.
Also add a Kconfig option to allow a mainboard to choose if this workaround is required, based on how the SD_VDD1_PWR_EN is implemented on it.
BUG=b:123350329
Change-Id: Iee262d7ecdf8c31362aec3d95dd9b3e8359e0c25 Signed-off-by: Rizwan Qureshi rizwan.qureshi@intel.com --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/acpi/scs.asl M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 3 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/31445/7