[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add the CnviDdrRfim configuration

[Ronak Kanabar (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph.
Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sumeet R Pawnikar, Subrata Banik, Sridhar Siricilla, Srinidhi N Kaushik, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/58132

to look at the new patch set (#9).

Change subject: soc/intel/alderlake: Add the CnviDdrRfim configuration
......................................................................

soc/intel/alderlake: Add the CnviDdrRfim configuration

FSP v2422_01 introduced new FSPM UPD CnviDdrRfim. Add CnviDdrRfim
config to control the CnviDdrRfim UPD from devicetree. Setting
CnviDdrRfim to 1 enable CNVi DDR RFIM

BUG=b:201724512
BRANCH=None
TEST=Build and boot brya with debug FSP and verify CnviDdrRfim UPD value.

Change-Id: Ia06c9ed77d78821fd4724046bae2f31c9d771518
Signed-off-by: Ronak Kanabar 
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/58132/9