Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82752?usp=email )
Change subject: cbmem_top: Change the return value to uintptr_t ......................................................................
cbmem_top: Change the return value to uintptr_t
Get rid of a lot of casts.
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/device/pci_device.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/hob_verify.c M src/include/cbmem.h M src/lib/imd_cbmem.c M src/mainboard/emulation/qemu-aarch64/mainboard.c M src/mainboard/emulation/qemu-riscv/mainboard.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/ironlake/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/northbridge/intel/x4x/northbridge.c M src/soc/amd/common/block/cpu/noncar/memmap.c M src/soc/amd/common/fsp/fsp_report_resources.c M src/soc/amd/stoneyridge/memmap.c M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/common/block/systemagent/memmap.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/memmap.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/uncore.c M src/soc/sifive/fu740/chip.c M src/vendorcode/amd/opensil/genoa_poc/memmap.c 36 files changed, 57 insertions(+), 81 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/82752/1
diff --git a/src/device/pci_device.c b/src/device/pci_device.c index af3355d..a2ad2b3 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -570,7 +570,7 @@ * one big range from cbmem_top to the configured limit. */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); - res->base = (uintptr_t)cbmem_top(); + res->base = cbmem_top(); res->limit = CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 39c3d26..9db1fe5 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -44,8 +44,7 @@ * writeback possible. */
- uintptr_t top_of_ram = (uintptr_t)cbmem_top(); - top_of_ram = ALIGN_UP(top_of_ram, 4 * MiB); + const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 4 * MiB);
set_range_uc(top_of_ram - 4 * MiB, 4 * MiB); set_range_uc(top_of_ram - 8 * MiB, 4 * MiB); @@ -78,7 +77,7 @@ * speed make them WB after CAR teardown. */ if (s3resume) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t top_of_ram = cbmem_top(); top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB);
postcar_frame_add_mtrr(pcf, top_of_ram - 4 * MiB, 4 * MiB, diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 7455d30..8bb9f33 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -12,12 +12,10 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); }
diff --git a/src/drivers/intel/fsp2_0/hob_verify.c b/src/drivers/intel/fsp2_0/hob_verify.c index ec526e8..8a0dadb 100644 --- a/src/drivers/intel/fsp2_0/hob_verify.c +++ b/src/drivers/intel/fsp2_0/hob_verify.c @@ -43,8 +43,8 @@ die("Space between FSP reserved region and BIOS TOLUM!\n"); }
- if (range_entry_end(&tolum) != (uintptr_t)cbmem_top()) { - printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %p: cbmem_top\n", + if (range_entry_end(&tolum) != cbmem_top()) { + printk(BIOS_CRIT, "TOLUM end: 0x%08llx != %ld: cbmem_top\n", range_entry_end(&tolum), cbmem_top()); die("Space between cbmem_top and BIOS TOLUM!\n"); } diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7af0110..de305ae 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -57,7 +57,7 @@ /* The assumption is made that the result of cbmem_top_romstage fits in the size of uintptr_t in the ramstage. */ extern uintptr_t _cbmem_top_ptr; -void *cbmem_top(void); +uintptr_t cbmem_top(void); /* With CONFIG_RAMSTAGE_CBMEM_TOP_ARG set, the result of cbmem_top is passed via * calling arguments to the next stage and saved in the global _cbmem_top_ptr * global variable. Only a romstage callback needs to be implemented by the diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 91c8621..a88cf98 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -15,17 +15,17 @@
static struct imd imd;
-void *cbmem_top(void) +uintptr_t cbmem_top(void) { if (ENV_CREATES_CBMEM) { static uintptr_t top; if (top) - return (void *)top; + return top; top = cbmem_top_chipset(); - return (void *)top; + return top; } if (ENV_POSTCAR || ENV_RAMSTAGE) - return (void *)_cbmem_top_ptr; + return _cbmem_top_ptr;
dead_code(); } @@ -55,7 +55,7 @@
/* The test is only effective on X86 and when address hits UC memory. */ if (ENV_X86) - quick_ram_check_or_die((uintptr_t)cbmem_top() - sizeof(u32)); + quick_ram_check_or_die(cbmem_top() - sizeof(u32)); }
void cbmem_initialize_empty_id_size(u32 id, u64 size) @@ -64,7 +64,7 @@
cbmem_top_init_once();
- imd_handle_init(&imd, cbmem_top()); + imd_handle_init(&imd, (void *)cbmem_top());
printk(BIOS_DEBUG, "CBMEM:\n");
@@ -95,7 +95,7 @@
cbmem_top_init_once();
- imd_handle_init(&imd, cbmem_top()); + imd_handle_init(&imd, (void *)cbmem_top());
if (imd_recover(&imd)) return 1; diff --git a/src/mainboard/emulation/qemu-aarch64/mainboard.c b/src/mainboard/emulation/qemu-aarch64/mainboard.c index a655989..2701072 100644 --- a/src/mainboard/emulation/qemu-aarch64/mainboard.c +++ b/src/mainboard/emulation/qemu-aarch64/mainboard.c @@ -43,7 +43,7 @@
mmio_range(dev, index++, VIRT_PCIE_ECAM_BASE, VIRT_PCIE_ECAM_SIZE);
- ram_from_to(dev, index++, (uintptr_t)_dram, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, (uintptr_t)_dram, cbmem_top()); }
struct device_operations qemu_aarch64_pci_domain_ops = { diff --git a/src/mainboard/emulation/qemu-riscv/mainboard.c b/src/mainboard/emulation/qemu-riscv/mainboard.c index e17ce13..61e8f98 100644 --- a/src/mainboard/emulation/qemu-riscv/mainboard.c +++ b/src/mainboard/emulation/qemu-riscv/mainboard.c @@ -11,7 +11,7 @@ die("No dev0; die\n"); }
- ram_from_to(dev, 0, (uintptr_t)_dram, (uintptr_t)cbmem_top()); + ram_from_to(dev, 0, (uintptr_t)_dram, cbmem_top()); }
struct chip_operations mainboard_ops = { diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index d036399..e2ba554 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -117,12 +117,10 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index dc18791..76ca4ee 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -81,7 +81,7 @@ reserved_ram_from_to(dev, idx++, 0xc0000, 1*MiB);
/* Report < 4GB memory */ - ram_range(dev, idx++, 1*MiB, (uintptr_t)cbmem_top()); + ram_range(dev, idx++, 1*MiB, cbmem_top());
/* TSEG */ uintptr_t tseg_base; @@ -91,10 +91,10 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tseg_base as unusable */ - if ((uintptr_t)cbmem_top() < tseg_base) { + if (cbmem_top() < tseg_base) { printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n", - tseg_base - (uintptr_t)cbmem_top()); - mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base); + tseg_base - cbmem_top()); + mmio_from_to(dev, idx++, cbmem_top(), tseg_base); }
/* graphic memory above TSEG */ diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 6b75caa..82e1d65 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -69,12 +69,10 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index 204e83b..8bdd5d9 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -53,10 +53,8 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache CBMEM region as WB. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index e0352fb..189f917 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -81,12 +81,10 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 79e9ee5..82f3843 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -34,7 +34,7 @@
/* Report the memory regions */ ram_range(dev, idx++, 0, 0xa0000); - ram_from_to(dev, idx++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, idx++, 1 * MiB, cbmem_top());
/* TSEG */ uintptr_t tseg_base; @@ -44,10 +44,10 @@
/* cbmem_top can be shifted downwards due to alignment. Mark the region between cbmem_top and tseg_base as unusable */ - if ((uintptr_t)cbmem_top() < tseg_base) { + if (cbmem_top() < tseg_base) { printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n", - tseg_base - (uintptr_t)cbmem_top()); - mmio_from_to(dev, idx++, (uintptr_t)cbmem_top(), tseg_base); + tseg_base - cbmem_top()); + mmio_from_to(dev, idx++, cbmem_top(), tseg_base); } if (tseg_base + tseg_size < tolud) mmio_from_to(dev, idx++, tseg_base + tseg_size, tolud); diff --git a/src/northbridge/intel/ironlake/memmap.c b/src/northbridge/intel/ironlake/memmap.c index bdb76c1..cb97c31 100644 --- a/src/northbridge/intel/ironlake/memmap.c +++ b/src/northbridge/intel/ironlake/memmap.c @@ -35,13 +35,11 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 967a59f..de2d840 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -86,13 +86,11 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* * Cache 8 MiB region below the top of RAM and 2 MiB above top of RAM to cover both * CBMEM and the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), northbridge_get_tseg_size(), MTRR_TYPE_WRBACK); diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index c24493a..573f1a8 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -69,7 +69,7 @@
/* Report the memory regions */ ram_range(dev, index++, 0, 0xa0000); - ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, 1 * MiB, cbmem_top()); uintptr_t tseg_base; size_t tseg_size; smm_region(&tseg_base, &tseg_size); @@ -77,8 +77,8 @@ mmio_range(dev, index++, gtt_base, gsm_size); mmio_range(dev, index++, igd_base, gms_size); printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOM: 0x%lx\n", - tseg_base - (uintptr_t)cbmem_top()); - reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base); + tseg_base - cbmem_top()); + reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
/* * If > 4GB installed then memory from TOLUD to 4GB diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index ac95ab5..174c286 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -67,7 +67,7 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top();
/* * Cache 8MiB below the top of ram. On sandybridge systems the top of diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 0b085cf..3e6cf11 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -84,12 +84,10 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache 8 MiB region below the top of RAM and 2 MiB above top of * RAM to cover both cbmem as the TSEG region. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(pcf, northbridge_get_tseg_base(), diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 4987cae..69eb951 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -45,7 +45,7 @@ ram_from_to(dev, index++, 0, 0xa0000); mmio_from_to(dev, index++, 0xa0000, 0xc0000); reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); - ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, 1 * MiB, cbmem_top());
/* * If >= 4GB installed then memory from TOLUD to 4GB @@ -57,7 +57,7 @@ size_t tseg_size; smm_region(&tseg_base, &tseg_size); mmio_from_to(dev, index++, tseg_base, tolud); - reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), tseg_base); + reserved_ram_from_to(dev, index++, cbmem_top(), tseg_base);
/* Reserve high memory where the NB BARs are up to 4GiB */ mmio_from_to(dev, index++, DEFAULT_HECIBAR, 4ull * GiB); diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 396260f..0626205 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -42,7 +42,7 @@ /* report SoC memory map up to cbmem_top */ void read_lower_soc_memmap_resources(struct device *dev, unsigned long *idx) { - const uint32_t mem_usable = (uintptr_t)cbmem_top(); + const uint32_t mem_usable = cbmem_top(); const struct memmap_early_dram *e = memmap_get_early_dram_usage(); const uintptr_t early_reserved_dram_start = e->base; const uintptr_t early_reserved_dram_end = e->base + e->size; @@ -76,7 +76,7 @@ if (CONFIG(PLATFORM_USES_FSP2_0)) { fsp_get_smm_region(start, size); } else { - *start = (uintptr_t)cbmem_top(); + *start = cbmem_top(); *size = CONFIG_SMM_TSEG_SIZE; }
diff --git a/src/soc/amd/common/fsp/fsp_report_resources.c b/src/soc/amd/common/fsp/fsp_report_resources.c index 37049fb..d5f4a029 100644 --- a/src/soc/amd/common/fsp/fsp_report_resources.c +++ b/src/soc/amd/common/fsp/fsp_report_resources.c @@ -9,7 +9,7 @@
void read_fsp_resources(struct device *dev, unsigned long *idx) { - const uint32_t mem_usable = (uintptr_t)cbmem_top(); + const uint32_t mem_usable = cbmem_top(); const struct hob_header *hob_iterator; const struct hob_resource *res;
diff --git a/src/soc/amd/stoneyridge/memmap.c b/src/soc/amd/stoneyridge/memmap.c index 32d6d96..f99c884 100644 --- a/src/soc/amd/stoneyridge/memmap.c +++ b/src/soc/amd/stoneyridge/memmap.c @@ -22,7 +22,7 @@
static uintptr_t smm_region_start(void) { - return (uintptr_t)cbmem_top(); + return cbmem_top(); }
static size_t smm_region_size(void) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index b51601b..9519713 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -259,7 +259,7 @@ { uint64_t uma_base = get_uma_base(); uint32_t uma_size = get_uma_size(); - uint32_t mem_useable = (uintptr_t)cbmem_top(); + uint32_t mem_useable = cbmem_top(); uint32_t tom = get_top_of_mem_below_4gb(); uint64_t high_tom = get_top_of_mem_above_4gb(); uint64_t high_mem_useable; diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index fc918f9..900d1a6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -125,7 +125,7 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
/* Cache the TSEG region */ diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index 43b96c1..9248534 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -29,13 +29,11 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 98c8016..770201b 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -47,13 +47,11 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); } diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index 04ab735..ca9f680 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -60,7 +60,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) { /* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */ - uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB); + const uintptr_t top_of_ram = ALIGN_UP(cbmem_top(), 8 * MiB);
/* * We need to make sure ramstage will be run cached. At this diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index e8e75d7..b2ae3cd 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -188,10 +188,9 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count) { uint64_t sa_map_values[MAX_MAP_ENTRIES]; - uintptr_t top_of_ram; int index = *resource_count;
- top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top();
/* 0 - > 0xa0000 */ ram_from_to(dev, index++, 0, 0xa0000); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..36ba62d 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -56,7 +56,7 @@ void soc_fill_gnvs(struct global_nvs *gnvs) { /* Top of Low Memory (start of resource allocation) */ - gnvs->tolm = (uintptr_t)cbmem_top(); + gnvs->tolm = cbmem_top();
/* MMIO Low/High & TSEG base and length */ gnvs->mmiob = (u32)get_top_of_low_memory(); diff --git a/src/soc/intel/denverton_ns/memmap.c b/src/soc/intel/denverton_ns/memmap.c index f607d0f..9576059 100644 --- a/src/soc/intel/denverton_ns/memmap.c +++ b/src/soc/intel/denverton_ns/memmap.c @@ -41,14 +41,12 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* * We need to make sure ramstage will be run cached. At this point exact * location of ramstage in cbmem is not known. Instruct postcar to cache * 16 megs under cbmem top which is a safe bet to cover ramstage. */ - top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 6c5149b..e8bcba7 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -240,10 +240,10 @@ reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB);
/* 0x100000 -> cbmem_top() */ - ram_from_to(dev, index++, 1 * MiB, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, 1 * MiB, cbmem_top());
/* cbmem_top() -> TSEG */ - mmio_from_to(dev, index++, (uintptr_t)cbmem_top(), mc_values[TSEG_REG]); + mmio_from_to(dev, index++, cbmem_top(), mc_values[TSEG_REG]);
/* TSEG -> TOLUD */ reserved_ram_from_to(dev, index++, mc_values[TSEG_REG], mc_values[TOLUD_REG]); diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index 8fe21e8..bf4c13e 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -30,7 +30,7 @@
void fill_postcar_frame(struct postcar_frame *pcf) { - const uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + const uintptr_t top_of_ram = cbmem_top(); uintptr_t cbmem_base; size_t cbmem_size;
diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index d2d4622..3c34505 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -125,7 +125,7 @@
static void configure_dpr(struct device *dev) { - const uintptr_t cbmem_top_mb = ALIGN_UP((uintptr_t)cbmem_top(), MiB) / MiB; + const uintptr_t cbmem_top_mb = ALIGN_UP(cbmem_top(), MiB) / MiB; union dpr_register dpr = { .raw = pci_read_config32(dev, VTD_LTDPR) };
/* The DPR lock bit has to be set sufficiently early. It looks like @@ -230,7 +230,7 @@ LOG_RESOURCE("low_ram", dev, res);
/* top_of_ram -> cbmem_top */ - res = ram_from_to(dev, index++, top_of_ram, (uintptr_t)cbmem_top()); + res = ram_from_to(dev, index++, top_of_ram, cbmem_top()); LOG_RESOURCE("cbmem_ram", dev, res);
/* Mark TSEG/SMM region as reserved */ @@ -246,7 +246,7 @@ * DPR has a 1M granularity so it's possible if cbmem_top is not 1M * aligned that some memory does not get marked as assigned. */ - res = reserved_ram_from_to(dev, index++, (uintptr_t)cbmem_top(), + res = reserved_ram_from_to(dev, index++, cbmem_top(), (dpr.top - dpr.size) * MiB); LOG_RESOURCE("unused_dram", dev, res);
diff --git a/src/soc/sifive/fu740/chip.c b/src/soc/sifive/fu740/chip.c index cd5052b..7829624 100644 --- a/src/soc/sifive/fu740/chip.c +++ b/src/soc/sifive/fu740/chip.c @@ -8,7 +8,7 @@ static void fu740_init(struct device *dev) { int index = 0; - ram_from_to(dev, index++, FU740_DRAM, (uintptr_t)cbmem_top()); + ram_from_to(dev, index++, FU740_DRAM, cbmem_top()); }
struct chip_operations soc_sifive_fu740_ops = { diff --git a/src/vendorcode/amd/opensil/genoa_poc/memmap.c b/src/vendorcode/amd/opensil/genoa_poc/memmap.c index bdf58e9..6261ad0 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/memmap.c +++ b/src/vendorcode/amd/opensil/genoa_poc/memmap.c @@ -87,7 +87,7 @@ void add_opensil_memmap(struct device *dev, unsigned long *idx) { // Account for UMA and TSEG - const uint32_t mem_usable = (uintptr_t)cbmem_top(); + const uint32_t mem_usable = cbmem_top(); const uint32_t top_mem = ALIGN_DOWN(get_top_of_mem_below_4gb(), 1 * MiB); if (mem_usable != top_mem) reserved_ram_from_to(dev, (*idx)++, mem_usable, top_mem);