[coreboot-gerrit] [M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs

[Lean Sheng Tan (Code Review)]

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email )

Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
......................................................................

soc/intel/xeon_sp/skx: Configure IOAPICs

FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.

Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.

TEST: Booted on ocp/tiogapass with correct GSI bases asigned
      matching the _PRT advertised GSI bases.

Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002

Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85170
Reviewed-by: Shuo Liu 
Tested-by: build bot (Jenkins) 
Reviewed-by: Lean Sheng Tan 
---
M src/soc/intel/xeon_sp/lpc_gen1.c
M src/soc/intel/xeon_sp/skx/Kconfig
M src/soc/intel/xeon_sp/skx/Makefile.mk
A src/soc/intel/xeon_sp/skx/ioapic.c
4 files changed, 74 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved
  Shuo Liu: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/lpc_gen1.c b/src/soc/intel/xeon_sp/lpc_gen1.c
index 9a1c629..b1d1efe 100644
--- a/src/soc/intel/xeon_sp/lpc_gen1.c
+++ b/src/soc/intel/xeon_sp/lpc_gen1.c
@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */

+#include <arch/ioapic.h>
 #include <console/console.h>
 #include <intelblocks/lpc_lib.h>

@@ -7,6 +8,9 @@
 {
    printk(BIOS_SPEW, "pch: lpc_init\n");

-	/* FSP configures IOAPIC and PCHInterrupt Config */
-	/* Should read back the ID to fill ACPI IOAPIC accordingly. */
+	if (CONFIG(SOC_INTEL_SKYLAKE_SP)) {
+		/* FSP only configures PCH IOAPIC, but it doesn't configure PCI IOAPICs.
+		 * Let coreboot handle all IOAPICs and assign unique IDs to each. */
+		register_new_ioapic_gsi0(IO_APIC_ADDR);
+	}
 }
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
index 1783c66..970dba3 100644
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
@@ -63,8 +63,4 @@
    string
    default "lbg"

-config XEON_SP_HAVE_IIO_IOAPIC
-	bool
-	default y
-
 endif
diff --git a/src/soc/intel/xeon_sp/skx/Makefile.mk b/src/soc/intel/xeon_sp/skx/Makefile.mk
index 456e932..624d60a 100644
--- a/src/soc/intel/xeon_sp/skx/Makefile.mk
+++ b/src/soc/intel/xeon_sp/skx/Makefile.mk
@@ -19,6 +19,7 @@
 ramstage-y += ../chip_gen1.c ../lpc_gen1.c
 ramstage-y += soc_util.c
 ramstage-y += cpu.c
+ramstage-y += ioapic.c
 ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
 ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
 ramstage-y += hob_display.c
diff --git a/src/soc/intel/xeon_sp/skx/ioapic.c b/src/soc/intel/xeon_sp/skx/ioapic.c
new file mode 100644
index 0000000..99a5368
--- /dev/null
+++ b/src/soc/intel/xeon_sp/skx/ioapic.c
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <arch/ioapic.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <soc/acpi.h>
+#include <soc/pci_devs.h>
+#include <soc/ramstage.h>
+#include <soc/chip_common.h>
+
+static void ioapic_read_resources(struct device *dev)
+{
+	pci_dev_read_resources(dev);
+
+	u16 abar = pci_read_config16(dev, APIC_ABAR);
+	if (!abar)
+		return;
+	const u32 addr = IO_APIC_ADDR | ((abar & 0xfff) << 8);
+
+	printk(BIOS_DEBUG, " %s: IOAPIC Address: 0x%x\n",
+	       dev_path(dev), addr);
+
+	mmio_range(dev, APIC_ABAR, addr, 0x100);
+}
+
+static void ioapic_init(struct device *dev)
+{
+	struct resource *resource;
+
+	pci_dev_init(dev);
+
+	/* See if there is a resource with the appropriate index. */
+	resource = probe_resource(dev, APIC_ABAR);
+	if (!resource)
+		return;
+
+	const union xeon_domain_path dn = {
+		.domain_path = dev_get_domain_id(dev)
+	};
+
+	/* 14nm Xeon-SP has up to 6 stacks per socket */
+	assert(dn.stack < MAX_LOGIC_IIO_STACK);
+
+	/* Assign socket specific GSI_BASE */
+	const u32 gsi_base = 24 + (dn.socket * MAX_LOGIC_IIO_STACK + dn.stack) * 8;
+
+	ioapic_create_dev(dev, resource->base, gsi_base);
+}
+
+static const unsigned short ioapic_ids[] = {
+	0x2036,
+	0x2026,
+	0
+};
+
+static struct device_operations ioapic_ops = {
+	.read_resources   = ioapic_read_resources,
+	.set_resources    = pci_dev_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = ioapic_init,
+};
+
+static const struct pci_driver ioapic_driver __pci_driver = {
+	.ops = &ioapic_ops,
+	.vendor = PCI_VID_INTEL,
+	.devices = ioapic_ids,
+};