Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56967 )
Change subject: soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default ......................................................................
soc/intel/common: Use CHIPSET_LOCKDOWN_COREBOOT by default
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it by default and remove its configuration from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured in the devicetree with something else, `CHIPSET_LOCKDOWN_COREBOOT` is used.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6 Signed-off-by: Felix Singer felixsinger@posteo.net --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/asrock/h110m/devicetree.cb M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb M src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb M src/mainboard/google/dedede/variants/baseboard/devicetree.cb M src/mainboard/google/deltaur/variants/baseboard/devicetree.cb M src/mainboard/google/drallion/variants/drallion/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/hatch/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/hp/280_g2/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/mainboard/intel/adlrvp/devicetree_m.cb M src/mainboard/intel/cedarisland_crb/devicetree.cb M src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb M src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kunimitsu/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb M src/mainboard/kontron/bsl6/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/ocp/deltalake/devicetree.cb M src/mainboard/ocp/tiogapass/devicetree.cb M src/mainboard/prodrive/hermes/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb M src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/siemens/chili/variants/base/devicetree.cb M src/mainboard/siemens/chili/variants/chili/devicetree.cb M src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/gaze15/devicetree.cb M src/mainboard/system76/lemp9/devicetree.cb M src/mainboard/system76/oryp5/devicetree.cb M src/mainboard/system76/oryp6/devicetree.cb M src/mainboard/system76/whl-u/devicetree.cb M src/soc/intel/common/block/include/intelblocks/cfg.h 59 files changed, 2 insertions(+), 160 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/56967/1
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1a1d012..5950dec 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -102,11 +102,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index 0acba3a..aed9184 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -41,10 +41,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 5938934..1d7dca6 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -1,6 +1,5 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, /* Touchpad */ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index 607e586..db4d1ac 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -31,10 +31,6 @@ .tdp_pl2_override = 30, }"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - register "SerialIoDevMode" = "{ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 13b3abc..023ace9 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -213,11 +213,6 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index eb85cb5..d19f627 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -83,14 +83,12 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio | #| I2C3 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb index 8a779bc..672d263 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brya/devicetree.cb @@ -81,7 +81,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | Fingerprint MCU | #| I2C0 | Audio and WFC | #| I2C1 | Touchscreen | @@ -91,7 +90,6 @@ #| | for TPM communication | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" register "common_soc_config" = "{ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 38b1da27..72eb62c 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -169,7 +169,6 @@ # Use below format to override value in overridetree.cb if required # format: # register "common_soc_config.<variable_name>" = "value" - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
# VR config settings # Imon Slope correction specified in 1/100 increment values. Range is 0-200. diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 4a0c49f..8c0098d 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -66,7 +66,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C2 | ISH ? | @@ -74,7 +73,6 @@ #| I2C5 | ISH ? | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, }, diff --git a/src/mainboard/google/drallion/variants/drallion/devicetree.cb b/src/mainboard/google/drallion/variants/drallion/devicetree.cb index 90bd260..561fe7c 100644 --- a/src/mainboard/google/drallion/variants/drallion/devicetree.cb +++ b/src/mainboard/google/drallion/variants/drallion/devicetree.cb @@ -162,7 +162,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -174,7 +173,6 @@ register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 180, diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 07b9100..8ea6539 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -159,14 +159,12 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Early TPM access | #| I2C2 | Touchpad | #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST_PLUS, .rise_time_ns = 98, diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index d33c9fd..e79f704 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -263,7 +263,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -272,7 +271,6 @@ #+-------------------+---------------------------+
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 3f7ce89..65e1014 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -83,11 +83,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 7d9d1e6..9dc43d4 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -199,7 +199,6 @@ # Use below format to override value in overridetree.cb if required # format: # register "common_soc_config.<variable_name>" = "value" - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT
device cpu_cluster 0 on device lapic 0 on end diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index e779ae4..ed7e202 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -158,7 +158,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -170,7 +169,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 98, diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index c5d8539..249183b 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -150,7 +150,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | H1 | #| I2C2 | Camera | @@ -160,7 +159,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 885fcbd..51da81a 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -191,7 +191,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -203,7 +202,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 3c7930d..098216d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -160,7 +160,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | @@ -173,7 +172,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 2b7debd..0d9c5bd 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -166,7 +166,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -179,7 +178,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 98, diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4ea4740..b3812d7 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -157,14 +157,12 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Trackpad | #| I2C5 | Audio | #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index df571aa..b44e867 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -150,7 +150,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | cr50 TPM. Early init is | #| | required to set up a BAR | @@ -162,7 +161,6 @@ #| pch_thermal_trip | PCH Trip Temperature | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .speed_config[0] = { diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 47709d9..a73bb17 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -151,7 +151,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -163,7 +162,6 @@ register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 52, diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index f035b79..f13a2af 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -152,7 +152,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| I2C0 | Touchscreen | #| I2C1 | Touchpad | #| I2C4 | H1 TPM | @@ -164,7 +163,6 @@ register "common_soc_config.pch_thermal_trip" = "77"
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 100, diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e2a84f8..5951c54 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -313,7 +313,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -325,7 +324,6 @@ #| I2C3 | Camera, SAR1 | #| I2C5 | Trackpad | #+-------------------+---------------------------+ - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT register "common_soc_config" = "{ .gspi[0] = { .speed_mhz = 1, diff --git a/src/mainboard/hp/280_g2/devicetree.cb b/src/mainboard/hp/280_g2/devicetree.cb index 98fccc9..47df4e1 100644 --- a/src/mainboard/hp/280_g2/devicetree.cb +++ b/src/mainboard/hp/280_g2/devicetree.cb @@ -1,10 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only
chip soc/intel/skylake - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - register "SerialIoDevMode" = "{ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, /* Routed to debug header */ }" diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index d4a2eb7..66e8553 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -177,7 +177,6 @@
# Intel Common SoC Config register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, }, diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb index b28f387..be94635 100644 --- a/src/mainboard/intel/adlrvp/devicetree_m.cb +++ b/src/mainboard/intel/adlrvp/devicetree_m.cb @@ -140,7 +140,6 @@
# Intel Common SoC Config register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, }, diff --git a/src/mainboard/intel/cedarisland_crb/devicetree.cb b/src/mainboard/intel/cedarisland_crb/devicetree.cb index 4691c05..e890082 100644 --- a/src/mainboard/intel/cedarisland_crb/devicetree.cb +++ b/src/mainboard/intel/cedarisland_crb/devicetree.cb @@ -1,9 +1,5 @@ chip soc/intel/xeon_sp/cpx
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 49c400f..12b1c47 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/cannonlake
- register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 415c0c9..1800541 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -163,10 +163,6 @@ # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb index 10284d4..c00502a 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb @@ -165,7 +165,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -173,7 +172,6 @@ #+-------------------+---------------------------+
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index cbee3ce..0d36f13 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -165,7 +165,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI1 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -173,7 +172,6 @@ #+-------------------+---------------------------+
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 262e27df..2120694 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -136,7 +136,6 @@ register "sdcard_cd_gpio" = "VGPIO_39"
register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index a5a51bf..e17c8b7 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -110,10 +110,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index 505a598..ba4835e 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -158,11 +158,6 @@ # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_A7"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 44ff902..7cf13ec 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -35,11 +35,6 @@
register "serirq_mode" = "SERIRQ_CONTINUOUS"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb index ab2c915..de3b4df 100644 --- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb @@ -130,7 +130,6 @@ #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -143,7 +142,6 @@ #| I2C5 | Trackpad | #+-------------------+---------------------------+ register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4e3d2e79..a82c0cc 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -151,7 +151,6 @@
# Intel Common SoC Config register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7f7e16b..9f4bb9a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -155,7 +155,6 @@
# Intel Common SoC Config register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[1] = { .speed_mhz = 1, .early_init = 1, diff --git a/src/mainboard/kontron/bsl6/devicetree.cb b/src/mainboard/kontron/bsl6/devicetree.cb index 910a49d..002f07e 100644 --- a/src/mainboard/kontron/bsl6/devicetree.cb +++ b/src/mainboard/kontron/bsl6/devicetree.cb @@ -2,10 +2,6 @@
chip soc/intel/skylake
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" register "PmConfigSlpS4MinAssert" = "SLP_S4_MIN_ASSERT_4S" register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 5e5c9be..0cf8abe 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -154,11 +154,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index e6f53be..f6b3c8b 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -48,10 +48,6 @@
register "cstate_states" = "CSTATES_C1C6"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb index a9bfe7f..1f7c9eb 100644 --- a/src/mainboard/ocp/tiogapass/devicetree.cb +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -40,10 +40,6 @@
register "gen2_dec" = "0x000c0ca1" # IPMI KCS
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index b276919..b7e89dc 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -1,6 +1,4 @@ chip soc/intel/cannonlake - register "common_soc_config.chipset_lockdown" = CHIPSET_LOCKDOWN_COREBOOT - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index dc73f91..3ef4250 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -191,11 +191,6 @@ [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ }"
- # Lock Down CHIPSET_LOCKDOWN_COREBOOT - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb index 6d0eb20..6288855 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb @@ -1,7 +1,6 @@ chip soc/intel/cannonlake # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, /* Touchpad */ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb index 836f4ac..6abe6b4 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb @@ -1,8 +1,4 @@ chip soc/intel/cannonlake - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }"
# CPU (soc/intel/cannonlake/cpu.c) # Power limit diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 84efd6a..5efb1e2 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -151,11 +151,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index a4951fe..655a089 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -154,11 +154,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - register "SerialIoDevMode" = "{ \ [PchSerialIoIndexI2C0] = PchSerialIoPci, \ [PchSerialIoIndexI2C1] = PchSerialIoPci, \ diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index e49ccd7..81dae2e 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -7,10 +7,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index f22e42c..b4d9970 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -7,10 +7,6 @@ register "PchHdaDspEnable" = "0" register "PchHdaAudioLinkHda" = "1"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb index f05f025..be98a15 100644 --- a/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb +++ b/src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb @@ -135,10 +135,6 @@ register "PchTsnGbeLinkSpeed" = "Tsn_2_5_Gbps" register "PchTsnGbeSgmiiEnable" = "1"
- register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1196629..6f627bb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -26,11 +26,6 @@ register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S"
- # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 5165f61..1aec60f 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -1,6 +1,5 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, // Touchpad I2C bus .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index 80f0ef4..536aa7d 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -1,6 +1,5 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, /* Touchpad */ .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/system76/oryp5/devicetree.cb b/src/mainboard/system76/oryp5/devicetree.cb index e8463ca..09c0884 100644 --- a/src/mainboard/system76/oryp5/devicetree.cb +++ b/src/mainboard/system76/oryp5/devicetree.cb @@ -1,6 +1,5 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, // Touchpad I2C bus .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 5d9c73b..24d894e 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -1,6 +1,5 @@ chip soc/intel/cannonlake register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, // Touchpad I2C bus .i2c[0] = { .speed = I2C_SPEED_FAST, diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb index ade42a4..da0f0b7 100644 --- a/src/mainboard/system76/whl-u/devicetree.cb +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -1,7 +1,6 @@ chip soc/intel/cannonlake # Lock Down register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .i2c[0] = { .speed = I2C_SPEED_FAST, .rise_time_ns = 80, diff --git a/src/soc/intel/common/block/include/intelblocks/cfg.h b/src/soc/intel/common/block/include/intelblocks/cfg.h index be2af4a..ab9c955 100644 --- a/src/soc/intel/common/block/include/intelblocks/cfg.h +++ b/src/soc/intel/common/block/include/intelblocks/cfg.h @@ -8,8 +8,8 @@ #include <intelblocks/mmc.h>
enum { - CHIPSET_LOCKDOWN_FSP = 0, /* FSP handles locking per UPDs */ - CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */ + CHIPSET_LOCKDOWN_COREBOOT = 0, /* coreboot handles locking */ + CHIPSET_LOCKDOWN_FSP, /* FSP handles locking per UPDs */ };
/*