[coreboot-gerrit] Change in coreboot[master]: soc/amd/common: Refactor and consolidate code for spi base

[Martin Roth (Code Review)]

Hello build bot (Jenkins), Raul Rangel, Furquan Shaikh, Eric Peers, Rob Barnes, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43307

to look at the new patch set (#5).

Change subject: soc/amd/common: Refactor and consolidate code for spi base
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soc/amd/common: Refactor and consolidate code for spi base

Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.

This patch consolidates all of that to a single saved value that gets
the LPC SPI BAR by default on X86, and allows the PSP to
set it to a different value.

BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.

Signed-off-by: Martin Roth 
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
---
M src/soc/amd/common/block/include/amdblocks/spi.h
M src/soc/amd/common/block/spi/fch_spi.c
M src/soc/amd/common/block/spi/fch_spi_ctrl.c
M src/soc/amd/stoneyridge/southbridge.c
4 files changed, 35 insertions(+), 37 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/43307/5