[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold

[John Zhao (Code Review)]

John Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43980 )

Change subject: soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/43980/4/src/soc/intel/tigerlake/fsp... 
PS4, Line 120: 	if (cpu_id == CPUID_TIGERLAKE_A0)
             : 		params->D3ColdEnable = 0;
> Do we still need this condition which we don't need eventually? […]

Without this check and configuration, A stepping D3Cold will be wrongly enabled now because no TcssD3ColdDisable is set across all platforms (Volteer/variants, RVP).